diff options
| author | Megan Wachs <megan@sifive.com> | 2018-08-29 15:45:11 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2018-08-29 15:47:54 -0700 |
| commit | 34ee883aef314f45b563b28b630a2b0b81086aea (patch) | |
| tree | afddabad461e5299c2084788a6a32766a24715ae /src/target/riscv/riscv.h | |
| parent | bdc43554934b12a340c82ceb6ce3eb0d1e61681b (diff) | |
| parent | b4b2ec7d2d143146226e7b2f06e1399ee560148d (diff) | |
| download | riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.zip riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.tar.gz riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.tar.bz2 | |
Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase
Diffstat (limited to 'src/target/riscv/riscv.h')
| -rw-r--r-- | src/target/riscv/riscv.h | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 1e7e328..419d051 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -7,7 +7,7 @@ struct riscv_program; #include "opcodes.h" #include "gdb_regs.h" -/* The register cache is staticly allocated. */ +/* The register cache is statically allocated. */ #define RISCV_MAX_HARTS 32 #define RISCV_MAX_REGISTERS 5000 #define RISCV_MAX_TRIGGERS 32 @@ -36,6 +36,11 @@ enum riscv_halt_reason { }; typedef struct { + struct target *target; + unsigned custom_number; +} riscv_reg_info_t; + +typedef struct { unsigned dtm_version; struct command_context *cmd_ctx; @@ -58,7 +63,9 @@ typedef struct { uint64_t saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS]; bool valid_saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS]; - /* The register cache points into here. */ + /* OpenOCD's register cache points into here. This is not per-hart because + * we just invalidate the entire cache when we change which hart is + * selected. */ uint64_t reg_cache_values[RISCV_MAX_REGISTERS]; /* Single buffer that contains all register names, instead of calling @@ -129,9 +136,6 @@ extern int riscv_command_timeout_sec; /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/ extern int riscv_reset_timeout_sec; -extern bool riscv_use_scratch_ram; -extern uint64_t riscv_scratch_ram_address; - extern bool riscv_prefer_sba; /* Everything needs the RISC-V specific info structure, so here's a nice macro @@ -257,7 +261,11 @@ int riscv_remove_breakpoint(struct target *target, int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint); int riscv_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); +int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address); int riscv_init_registers(struct target *target); +void riscv_semihosting_init(struct target *target); +int riscv_semihosting(struct target *target, int *retval); + #endif |