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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-10-23 12:55:10 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-10-23 12:55:10 +0000
commit5df88ed3a1afb0334318a15d46474016b6e6d837 (patch)
treecd9a7fda9f9957e74af45a5579a2d09aadb229f4 /src/target/arm_simulator.c
parentc3e213a6e102ed7445fee1aba40bcf1c4531795a (diff)
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hontor <hontor@126.com> - fix simulation step errors
git-svn-id: svn://svn.berlios.de/openocd/trunk@1097 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm_simulator.c')
-rw-r--r--src/target/arm_simulator.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 07e1801..2873a5a 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -533,9 +533,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
load_address = Rn;
}
- if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+ if((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
{
- return retval;
+ if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+ {
+ return retval;
+ }
}
if (dry_run_pc)
@@ -599,7 +602,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- target_read_u32(target, Rn, &load_values[i]);
+ if((!dry_run_pc) || (i == 15))
+ {
+ target_read_u32(target, Rn, &load_values[i]);
+ }
Rn += 4;
}
}