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| author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-02-05 12:03:04 +0000 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-02-06 11:00:36 +0000 |
| commit | 374127301ec1d72033b9d573b72c7abdfd61990d (patch) | |
| tree | b56f5f4bba1718f9ac482d1fabdff18f5d170196 /src/target/arm_opcodes.h | |
| parent | de0130a0aad83c1ef692ee4d68ab996a8668424d (diff) | |
| download | riscv-openocd-374127301ec1d72033b9d573b72c7abdfd61990d.zip riscv-openocd-374127301ec1d72033b9d573b72c7abdfd61990d.tar.gz riscv-openocd-374127301ec1d72033b9d573b72c7abdfd61990d.tar.bz2 | |
build: cleanup src/target directory
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
Diffstat (limited to 'src/target/arm_opcodes.h')
| -rwxr-xr-x | src/target/arm_opcodes.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index 9a48e6d..12a9ca8 100755 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -90,8 +90,8 @@ * Rd: register to load * Rn: base register */ -#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) - +#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) + /* Load Register Halfword Immediate Post-Index * Rd: register to load * Rn: base register @@ -108,7 +108,7 @@ * Rd: register to store * Rn: base register */ -#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) +#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) /* Store register Halfword Immediate Post-Index * Rd: register to store |