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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:38:34 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:38:34 -0800 |
| commit | ff810723e051ed1f86cffcb565ade6b4d1fc50c8 (patch) | |
| tree | bb114d521b84926cd3ce1b4975275c192a8f074a /src/target/arm920t.c | |
| parent | 5706fd7860ea01c591ecf74880a5a5e04e6df22e (diff) | |
| download | riscv-openocd-ff810723e051ed1f86cffcb565ade6b4d1fc50c8.zip riscv-openocd-ff810723e051ed1f86cffcb565ade6b4d1fc50c8.tar.gz riscv-openocd-ff810723e051ed1f86cffcb565ade6b4d1fc50c8.tar.bz2 | |
ARM: define two register utilities
Define arm_reg_current() ... returning handle to a given register,
and encapsulating the current mode's register shadowing. It's got
one current use, for reporting the current register set to GDB.
This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
nastiness, saving a bit of code.
Define and use arm_set_cpsr() ... initially it updates the cached
CPSR and sets up state used by arm_reg_current(), plus any SPSR
handle. (Later: can also set up for T and J bits.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm920t.c')
| -rw-r--r-- | src/target/arm920t.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 9cd491f..739df3e 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -596,18 +596,20 @@ int arm920t_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3); + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); armv4_5->cpsr->dirty = 1; - armv4_5->cpsr->valid = 1; + armv4_5->core_state = ARMV4_5_STATE_ARM; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; |