diff options
| author | Tim Newsome <tim@sifive.com> | 2021-04-13 11:22:43 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2021-04-13 11:26:25 -0700 |
| commit | 7420382a4d9453bf4bf72f2e42728136f9a3b7bb (patch) | |
| tree | 4aa04d3b401b9b9da8c29fda93e6ff23a70b29f1 /src/target/arc.c | |
| parent | 05e962e03a9642f883c0a91c38409ba89ad4fa7c (diff) | |
| parent | 0f06d943366154963c6f5eb70f52e70f64fe5c71 (diff) | |
| download | riscv-openocd-7420382a4d9453bf4bf72f2e42728136f9a3b7bb.zip riscv-openocd-7420382a4d9453bf4bf72f2e42728136f9a3b7bb.tar.gz riscv-openocd-7420382a4d9453bf4bf72f2e42728136f9a3b7bb.tar.bz2 | |
Merge branch 'master' into from_upstream
Conflicts:
.github/workflows/snapshot.yml
NEWS
configure.ac
contrib/loaders/checksum/riscv_crc.c
jimtcl
src/helper/time_support.h
src/jtag/drivers/arm-jtag-ew.c
src/rtos/FreeRTOS.c
src/target/image.c
src/target/riscv/riscv.c
Change-Id: I043624ba540d4672fc123dddb2066bcb9c6b5a05
Diffstat (limited to 'src/target/arc.c')
| -rw-r--r-- | src/target/arc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arc.c b/src/target/arc.c index 8e56845..694ac6f 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -227,7 +227,7 @@ static int arc_get_register(struct reg *reg) if (desc->is_core) { /* Accessing to R61/R62 registers causes Jtag hang */ - if (desc->arch_num == CORE_R61_NUM || desc->arch_num == CORE_R62_NUM) { + if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) { LOG_ERROR("It is forbidden to read core registers 61 and 62."); return ERROR_FAIL; } @@ -267,8 +267,8 @@ static int arc_set_register(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; /* Accessing to R61/R62 registers causes Jtag hang */ - if (desc->is_core && (desc->arch_num == CORE_R61_NUM || - desc->arch_num == CORE_R62_NUM)) { + if (desc->is_core && (desc->arch_num == ARC_R61 || + desc->arch_num == ARC_R62)) { LOG_ERROR("It is forbidden to write core registers 61 and 62."); return ERROR_FAIL; } |