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authordrath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2006-11-22 13:03:10 +0000
committerdrath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2006-11-22 13:03:10 +0000
commite9297b40b994f071474210e7d9e224d50e25fcaf (patch)
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parent03e8f264f4c66baec9b86778d3488b23e0a8c0b6 (diff)
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- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration
- added support for loading .bit files into Xilinx Virtex-II devices - added support for the Gateworks GW16012 JTAG dongle - merged CFI fixes from XScale branch - a few minor fixes git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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+INCLUDES = -I$(top_srcdir)/src/server -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag $(all_includes)
+METASOURCES = AUTO
+noinst_LIBRARIES = libpld.a
+noinst_HEADERS = pld.h xilinx_bit.h virtex2.h
+libpld_a_SOURCES = pld.c xilinx_bit.c virtex2.c