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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-19 22:59:58 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-20 00:11:51 +0300 |
| commit | 967510cb1ddebd379ae01b941038285077c5113f (patch) | |
| tree | 78dc72109a6734bb9d93ad26519136299f43bbb6 /src/openocd.c | |
| parent | 3991492cc101f4289be06ec7dc23c6ad7748a74a (diff) | |
| download | riscv-openocd-967510cb1ddebd379ae01b941038285077c5113f.zip riscv-openocd-967510cb1ddebd379ae01b941038285077c5113f.tar.gz riscv-openocd-967510cb1ddebd379ae01b941038285077c5113f.tar.bz2 | |
target/riscv/riscv-011.c: fix access to non-existent register
`reg` is a number in register cache, as evident by the following call to
`reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in
setting cache value for another register, which does not exist, and
causes a segfault if all non-existent registers are not allocated a
value (`reg->value == NULL`).
Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Diffstat (limited to 'src/openocd.c')
0 files changed, 0 insertions, 0 deletions