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| author | Andrey Yurovsky <yurovsky@gmail.com> | 2014-02-25 22:18:03 -0800 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-03-04 20:18:37 +0000 |
| commit | 8e44a9663df314ad527cca6687ea362c72e84a3f (patch) | |
| tree | 21f2ab1ba60aeebcdfcca3b0ecb14d94c39564bc /src/flash/nor/at91sam4.c | |
| parent | d585c1627a14e7789aa659d73c43a1408657b041 (diff) | |
| download | riscv-openocd-8e44a9663df314ad527cca6687ea362c72e84a3f.zip riscv-openocd-8e44a9663df314ad527cca6687ea362c72e84a3f.tar.gz riscv-openocd-8e44a9663df314ad527cca6687ea362c72e84a3f.tar.bz2 | |
Add support for the Atmel SAMG53
flash: at91sam4: add support for the SAMG53 family (this also covers the
SAMG51). The SAMG5x parts have an EEFC (enhanced embedded flash controller)
which seems to be identical to the EFC that the sam4 driver supports.
Add a script for the Xplained Pro G53 board, this has the onboard CMSIS-DAP
debugger and a SAMG53N19. Tested on this board and chip combination.
Change-Id: I12af50402cd2069b3c7380d92e6fe54816d6c045
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1974
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/flash/nor/at91sam4.c')
| -rw-r--r-- | src/flash/nor/at91sam4.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index cda74f9..84d09c2 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -504,6 +504,41 @@ static const struct sam4_chip_details all_sam4_details[] = { }, }, + /* at91samg53n19 */ + { + .chipid_cidr = 0x247e0ae0, + .name = "at91samg53n19", + .total_flash_size = 512 * 1024, + .total_sram_size = 96 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + +/* .bank[0] = {*/ + { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 512 * 1024, + .nsectors = 64, + .sector_size = 8192, + .page_size = 512, + }, +/* .bank[1] = {*/ + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + } + }, + /* terminate */ { .chipid_cidr = 0, @@ -1078,6 +1113,10 @@ static const struct archnames { unsigned value; const char *name; } archnames[] { 0x3B, "CAP11 Series" }, { 0x40, "AT91x40 Series" }, { 0x42, "AT91x42 Series" }, + { 0x43, "SAMG51 Series" + }, + { 0x47, "SAMG53 Series" + }, { 0x55, "AT91x55 Series" }, { 0x60, "AT91SAM7Axx Series" }, { 0x61, "AT91SAM7AQxx Series" }, |