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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2019-12-16 15:21:33 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2020-01-02 21:18:22 +0000 |
| commit | bc0667c2371b7b142356aaab7f125c30f76168fd (patch) | |
| tree | f7cf2dbf969d580651ed3938f146c61dd5ea79a8 /doc | |
| parent | 9c5c3ab3d60285fb7976341031705d0340c5fe33 (diff) | |
| download | riscv-openocd-bc0667c2371b7b142356aaab7f125c30f76168fd.zip riscv-openocd-bc0667c2371b7b142356aaab7f125c30f76168fd.tar.gz riscv-openocd-bc0667c2371b7b142356aaab7f125c30f76168fd.tar.bz2 | |
flash/nor/stm32h7: (minor) use proper variable names and enhance logging
-fsize_base should be fsize_addr as it is the address of FLASH_SIZE register
-flash_base should be flash_regs_base to avoid confusion with flash block start
-add LOG_ERROR to functions stm32x_[read|write]_flash_reg(...)
Change-Id: I86f035314bcd616fc0bdf445692d945a85c15481
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5362
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'doc')
0 files changed, 0 insertions, 0 deletions