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| author | Andreas Bolsch <hyphen0break@gmail.com> | 2018-12-16 17:30:41 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2020-03-16 15:25:10 +0000 |
| commit | ba131f30a0798d97729f9517c136d32f58f57571 (patch) | |
| tree | e11c20398df97a20de5b20421e58471dd853862f /doc | |
| parent | e03de33c412b366f3dd45c447410dcc1df3b4b82 (diff) | |
| download | riscv-openocd-ba131f30a0798d97729f9517c136d32f58f57571.zip riscv-openocd-ba131f30a0798d97729f9517c136d32f58f57571.tar.gz riscv-openocd-ba131f30a0798d97729f9517c136d32f58f57571.tar.bz2 | |
Flash driver for STM32G0xx and STM32G4xx
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 711171a..97c5a72 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -6892,8 +6892,10 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @deffn {Flash Driver} stm32l4x -All members of the STM32L4 and STM32WB microcontroller families from STMicroelectronics -include internal flash and use ARM Cortex-M4 cores. +All members of the STM32L4, STM32L4+, STM32WB and STM32G4 +microcontroller families from STMicroelectronics include internal flash +and use ARM Cortex-M4 cores. +Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @@ -6903,7 +6905,8 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by -the flash driver. +the flash driver. However, specifying a wrong value might lead to a completely +wrong flash layout, so this feature must be used carefully. @example flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME @@ -6960,7 +6963,7 @@ This will effectively write protect all sectors in flash bank 1. @end deffn @deffn Command {stm32l4x option_load} num -Forces a re-load of the option byte registers. Will cause a reset of the device. +Forces a re-load of the option byte registers. Will cause a system reset of the device. The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @end deffn |