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authorntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-08-20 10:51:45 +0000
committerntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-08-20 10:51:45 +0000
commita3325f1dc4fd6246706723afd29bb4d69e62bddd (patch)
tree338bc045c2e7bc24040028fab6d9819e2f775b41 /doc
parent7e94e2e8b18a382455a9e5965f813d781dc0218a (diff)
downloadriscv-openocd-a3325f1dc4fd6246706723afd29bb4d69e62bddd.zip
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- added missing parport configs to texi
- remove spaces from last patch git-svn-id: svn://svn.berlios.de/openocd/trunk@951 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi18
1 files changed, 16 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 80bb33e..f16e9e4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -437,13 +437,20 @@ Currently supported cables are
@cindex wiggler
The original Wiggler layout, also supported by several clones, such
as the Olimex ARM-JTAG
+@item @b{wiggler2}
+@cindex wiggler2
+Same as original wiggler except an led is fitted on D5.
+@item @b{wiggler_ntrst_inverted}
+@cindex wiggler_ntrst_inverted
+Same as original wiggler except TRST is inverted.
@item @b{old_amt_wiggler}
@cindex old_amt_wiggler
The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
version available from the website uses the original Wiggler layout ('@var{wiggler}')
@item @b{chameleon}
@cindex chameleon
-The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
+The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
+program the Chameleon itself, not a connected target.
@item @b{dlc5}
@cindex dlc5
The Xilinx Parallel cable III.
@@ -454,7 +461,14 @@ This is also the layout used by the HollyGates design
(see @uref{http://www.lartmaker.nl/projects/jtag/}).
@item @b{flashlink}
@cindex flashlink
-The ST Parallel cable.
+The ST Parallel cable.
+@item @b{arm-jtag}
+@cindex arm-jtag
+Same as original wiggler except SRST and TRST connections reversed and
+TRST is also inverted.
+@item @b{altium}
+@cindex altium
+Altium Universal JTAG cable.
@end itemize
@item @b{parport_write_on_exit} <@var{on|off}>
@cindex parport_write_on_exit