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author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-18 04:08:51 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-18 04:08:51 +0000 |
commit | 8f9f5c189bc64c8cd8a14b4dfb156e3382ca050a (patch) | |
tree | 7852d96e89e87614eeaedd0dbd1fe75c65555fe0 /doc | |
parent | 1642dd2ea0ed1cefb49f886425043aace9a68504 (diff) | |
download | riscv-openocd-8f9f5c189bc64c8cd8a14b4dfb156e3382ca050a.zip riscv-openocd-8f9f5c189bc64c8cd8a14b4dfb156e3382ca050a.tar.gz riscv-openocd-8f9f5c189bc64c8cd8a14b4dfb156e3382ca050a.tar.bz2 |
David Brownell <david-b@pacbell.net>:
The PLD stuff hasn't been documented yet. It's just Virtex2 for now,
but it looks like adding others would be easy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2273 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'doc')
-rw-r--r-- | doc/openocd.texi | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 0a89d3f..88d4abd 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -73,6 +73,7 @@ Free Documentation License''. * CPU Configuration:: CPU Configuration * Flash Commands:: Flash Commands * NAND Flash Commands:: NAND Flash Commands +* PLD/FPGA Commands:: PLD/FPGA Commands * General Commands:: General Commands * Architecture and Core Commands:: Architecture and Core Commands * JTAG Commands:: JTAG Commands @@ -3981,6 +3982,62 @@ or @code{read_page} methods, so @command{nand raw_access} won't change any behavior. @end deffn +@node PLD/FPGA Commands +@chapter PLD/FPGA Commands +@cindex PLD +@cindex FPGA + +Programmable Logic Devices (PLDs) and the more flexible +Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware. +OpenOCD can support programming them. +Although PLDs are generally restrictive (cells are less functional, and +there are no special purpose cells for memory or computational tasks), +they share the same OpenOCD infrastructure. +Accordingly, both are called PLDs here. + +@section PLD/FPGA Configuration and Commands + +As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND), +OpenOCD maintains a list of PLDs available for use in various commands. +Also, each such PLD requires a driver. + +They are referenced by the number shown by the @command{pld devices} command, +and new PLDs are defined by @command{pld device driver_name}. + +@deffn {Config Command} {pld device} driver_name tap_name [driver_options] +Defines a new PLD device, supported by driver @var{driver_name}, +using the TAP named @var{tap_name}. +The driver may make use of any @var{driver_options} to configure its +behavior. +@end deffn + +@deffn {Command} {pld devices} +Lists the PLDs and their numbers. +@end deffn + +@deffn {Command} {pld load} num filename +Loads the file @file{filename} into the PLD identified by @var{num}. +The file format must be inferred by the driver. +@end deffn + +@section PLD/FPGA Drivers, Options, and Commands + +Drivers may support PLD-specific options to the @command{pld device} +definition command, and may also define commands usable only with +that particular type of PLD. + +@deffn {FPGA Driver} virtex2 +Virtex-II is a family of FPGAs sold by Xilinx. +It supports the IEEE 1532 standard for In-System Configuration (ISC). +No driver-specific PLD definition options are used, +and one driver-specific command is defined. + +@deffn {Command} {virtex2 read_stat} num +Reads and displays the Virtex-II status register (STAT) +for FPGA @var{num}. +@end deffn +@end deffn + @node General Commands @chapter General Commands @cindex commands |