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authorasier70 <asier70@gmail.com>2021-04-12 14:09:36 +0200
committerTomas Vanek <vanekt@fbl.cz>2021-05-02 22:39:38 +0100
commit64a3e7ba4f47c5340543d9a5cadd41bc45d93c93 (patch)
treebecc840b87051aa1d0481c292a89c774e8dd85ef /doc
parent87c90393fedc8bb278d189aa53bcd93f4892012b (diff)
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flash/nor/stm32f1x: Add support for GD32F1x0/3x0
Nowadays, when it's difficult to buy STM32F030, the use of GD32F130 seems to be an interesting functional alternative. This is cortex-M3 and it works with the stm32f1x driver, but unfortunately not fully. The main difference is another offset of user option bits (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register (FLASH_OBR/FMC_OBSTAT 0x4002201C). Any use of functions like lock or unlock results in change default values of the those bits stored in flash. Thus broken microcontroller is malfunctioning, e.g. flash block programming is interrupted by unexpected active hardware watchog (after 0.4s). This patch is a simplified version of #4592 done by Dominik Peklo (http://openocd.zylin.com/#/c/4592/). GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID with STM32F101/2/3 medium-density line, however they use a REV_ID different from any STM32 device, so can be succesfully detected. Change-Id: I252cdf738d94983b70676a3497326f90c329e292 Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com> Reviewed-on: http://openocd.zylin.com/6164 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi3
1 files changed, 2 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index d717311..a05f85d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6927,7 +6927,8 @@ applied to all of them.
@deffn {Flash Driver} {stm32f1x}
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
-from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
+from STMicroelectronics and all members of the GD32F1x0 and GD32F3x0 microcontroller
+families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.