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| author | Jan Matyas <matyas@codasip.com> | 2020-04-01 11:58:20 +0200 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2020-04-09 11:06:39 +0100 |
| commit | 25efc150694042b349b8df1ff7c41f16955c5288 (patch) | |
| tree | a01e4feb8433dc306dd6878ce4174651058f90ac /doc | |
| parent | 0a804222da63c5f849efa23b019a59e2dea76842 (diff) | |
| download | riscv-openocd-25efc150694042b349b8df1ff7c41f16955c5288.zip riscv-openocd-25efc150694042b349b8df1ff7c41f16955c5288.tar.gz riscv-openocd-25efc150694042b349b8df1ff7c41f16955c5288.tar.bz2 | |
target: added events TARGET_EVENT_STEP_START and _END
Events TARGET_EVENT_STEP_START and TARGET_EVENT_STEP_END
have been added - analogous to already existing events
TARGET_EVENT_RESUME_*.
This is an example of a concrete use case where having
these events is important:
In RISC-V processors without Debug Program Buffer, OpenOCD
cannot execute fence/fence.i when resuming or single-
stepping. With these events implemented, the user can
instead provide custom operations to achieve that same
effect prior to resuming the processor.
Change-Id: I786348ff08940759d99b0f24e9e0ed5a44581094
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/5551
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 250db32..0c58a68 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4924,6 +4924,10 @@ when reset disables PLLs needed to use a fast clock. @* After all targets have resumed @item @b{resumed} @* Target has resumed +@item @b{step-start} +@* Before a target is single-stepped +@item @b{step-end} +@* After single-step has completed @item @b{trace-config} @* After target hardware trace configuration was changed @end itemize |