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| author | Christopher Head <chead@zaber.com> | 2018-08-01 10:21:15 -0700 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2019-04-10 20:05:32 +0100 |
| commit | a4ac56152d9fc13c3fa479397407d9b86ffb13d8 (patch) | |
| tree | 3b543d588e490ba2e6f960695380d35427508a6c /doc/openocd.texi | |
| parent | 5b263d7b0c71d2560af5dabbeec051b807d9e6a3 (diff) | |
| download | riscv-openocd-a4ac56152d9fc13c3fa479397407d9b86ffb13d8.zip riscv-openocd-a4ac56152d9fc13c3fa479397407d9b86ffb13d8.tar.gz riscv-openocd-a4ac56152d9fc13c3fa479397407d9b86ffb13d8.tar.bz2 | |
target/cortex_m: Implement maskisr steponly option
`maskisr steponly` disables interrupts during single-stepping but
enables them during normal execution. This can be used as a partial
workaround for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610)
and Cortex-M7 with FPU (AT611) Software Developer Errata Notice" from
ARM for further details.
Change-Id: I797a14e4d43f6dcb3706528ee4ab452846ebf133
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4673
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'doc/openocd.texi')
| -rw-r--r-- | doc/openocd.texi | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 81a9135..a5037b2 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9078,7 +9078,7 @@ Enable or disable trace output for all ITM stimulus ports. @subsection Cortex-M specific commands @cindex Cortex-M -@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}) +@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly}) Control masking (disabling) interrupts during target step/resume. The @option{auto} option handles interrupts during stepping in a way that they @@ -9088,6 +9088,11 @@ the next instruction where the core was halted. After the step interrupts are enabled again. If the interrupt handlers don't complete within 500ms, the step command leaves with the core running. +The @option{steponly} option disables interrupts during single-stepping but +enables them during normal execution. This can be used as a partial workaround +for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with +FPU (AT611) Software Developer Errata Notice" from ARM for further details. + Note that a free hardware (FPB) breakpoint is required for the @option{auto} option. If no breakpoint is available at the time of the step, then the step is taken with interrupts enabled, i.e. the same way the @option{off} option |