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| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2012-01-25 01:10:24 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-01-30 20:01:42 +0000 |
| commit | 81b4ef6ee52fd0e897f4c2ecc6a173161abb930f (patch) | |
| tree | 7510ae4d6aeae9f02baa0cb4c6fa129b2c334db8 /contrib/loaders | |
| parent | 61f3d4b7e42897fb1570bd4307137833cce0f7ba (diff) | |
| download | riscv-openocd-81b4ef6ee52fd0e897f4c2ecc6a173161abb930f.zip riscv-openocd-81b4ef6ee52fd0e897f4c2ecc6a173161abb930f.tar.gz riscv-openocd-81b4ef6ee52fd0e897f4c2ecc6a173161abb930f.tar.bz2 | |
stm32f1x: fix bug in flash loader and restrict instruction set to armv6-m
Correct the offset to the read pointer when clearing it on error.
Also restrict the instruction set to armv6-m so the flash driver can be
used on Cortex-M0 parts with the same flash controller.
Change-Id: I380f9dabcc41fb6e4d43a7e02f355e2381913f39
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/399
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'contrib/loaders')
| -rw-r--r-- | contrib/loaders/flash/stm32f1x.S | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/contrib/loaders/flash/stm32f1x.S b/contrib/loaders/flash/stm32f1x.S index 125c76a..e83d8c1 100644 --- a/contrib/loaders/flash/stm32f1x.S +++ b/contrib/loaders/flash/stm32f1x.S @@ -20,7 +20,7 @@ .text .syntax unified - .cpu cortex-m3 + .cpu cortex-m0 .thumb .thumb_func .global write @@ -34,6 +34,7 @@ * Clobbered: * r5 - rp * r6 - wp, tmp + * r7 - tmp */ #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */ @@ -48,24 +49,31 @@ wait_fifo: beq wait_fifo movs r6, #1 /* set PG flag to enable flash programming */ str r6, [r0, #STM32_FLASH_CR_OFFSET] - ldrh r6, [r5], #2 /* "*target_address++ = *rp++" */ - strh r6, [r4], #2 + ldrh r6, [r5] /* "*target_address++ = *rp++" */ + strh r6, [r4] + adds r5, #2 + adds r4, #2 busy: ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */ - tst r6, #1 + movs r7, #1 + tst r6, r7 bne busy - tst r6, #0x14 /* check the error bits */ + movs r7, #0x14 /* check the error bits */ + tst r6, r7 bne error cmp r5, r3 /* wrap rp at end of buffer */ - it cs - addcs r5, r2, #8 + bcc no_wrap + mov r5, r2 + adds r5, #8 +no_wrap: str r5, [r2, #4] /* store rp */ subs r1, r1, #1 /* decrement halfword count */ - cbz r1, exit /* loop if not done */ - b wait_fifo + cmp r1, #0 + beq exit /* loop if not done */ + b wait_fifo error: movs r0, #0 - str r0, [r2, #2] /* set rp = 0 on error */ + str r0, [r2, #4] /* set rp = 0 on error */ exit: mov r0, r6 /* return status in r0 */ bkpt #0 |