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| author | IS2T <devel@is2t.com> | 2013-06-19 08:03:17 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-07-01 08:39:36 +0000 |
| commit | 34e8d1a50d9ee965e2efa4aae6e2e97caef37c23 (patch) | |
| tree | f3bab2e71bc54146690943a58588fa464ef02e6b /contrib/loaders/flash | |
| parent | 434afb370f92898b8803a4883f75ecb9f3f3d931 (diff) | |
| download | riscv-openocd-34e8d1a50d9ee965e2efa4aae6e2e97caef37c23.zip riscv-openocd-34e8d1a50d9ee965e2efa4aae6e2e97caef37c23.tar.gz riscv-openocd-34e8d1a50d9ee965e2efa4aae6e2e97caef37c23.tar.bz2 | |
Support for SST 39VF3201C NOR flash
* Add Thumb-2 code to write flash memories that don't support DQ5 polling
* Make sure default values for unlock commands are set even if there is no PRI information given by the flash
* Add a fixup to disable DQ5 polling for the SST 39VF3201C
Change-Id: Ib08cf20547d0f500d5f78241521e6b49050c3d40
Signed-off-by: IS2T development team <dev.is2t@gmail.com>
Reviewed-on: http://openocd.zylin.com/1449
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'contrib/loaders/flash')
| -rw-r--r-- | contrib/loaders/flash/armv7m_cfi_span_16_dq7.s | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s new file mode 100644 index 0000000..5b29a3b --- /dev/null +++ b/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2005, 2007 by Dominic Rath * + * Dominic.Rath@gmx.de * + * Copyright (C) 2010 Spencer Oliver * + * spen@spen-soft.co.uk * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + ***************************************************************************/ + + .text + .syntax unified + .arch armv7-m + .thumb + .thumb_func + + .align 2 + +/* input parameters - */ +/* R0 = source address */ +/* R1 = destination address */ +/* R2 = number of writes */ +/* R3 = flash write command */ +/* R4 = constant to mask DQ7 bits */ +/* output parameters - */ +/* R5 = 0x80 ok 0x00 bad */ +/* temp registers - */ +/* R6 = value read from flash to test status */ +/* R7 = holding register */ +/* unlock registers - */ +/* R8 = unlock1_addr */ +/* R9 = unlock1_cmd */ +/* R10 = unlock2_addr */ +/* R11 = unlock2_cmd */ + +code: + ldrh r5, [r0], #2 + strh r9, [r8] + strh r11, [r10] + strh r3, [r8] + strh r5, [r1] + nop +busy: + ldrh r6, [r1] + eor r7, r5, r6 + ands r7, r4, r7 + bne busy + subs r2, r2, #1 /* 0x1 */ + beq success + add r1, r1, #2 /* 0x2 */ + b code + +success: + mov r5, #128 /* 0x80 */ + b done + +done: + bkpt #0 + + .end |