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| author | Tim Newsome <tim@sifive.com> | 2021-06-21 14:37:41 -0700 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-07-02 17:13:52 +0100 |
| commit | 6ad89d61af681e11960082a906357d8e8c3396a1 (patch) | |
| tree | a1416e9908ab54f5c510000846d06bd2340f4adc /ChangeLog | |
| parent | c8e643fd9f09849b341942d11866ab45bc7c99a3 (diff) | |
| download | riscv-openocd-6ad89d61af681e11960082a906357d8e8c3396a1.zip riscv-openocd-6ad89d61af681e11960082a906357d8e8c3396a1.tar.gz riscv-openocd-6ad89d61af681e11960082a906357d8e8c3396a1.tar.bz2 | |
Add RTOS memory read/write functions.
If not implemented, these specify to regular target read/write. However,
if individual threads in an RTOS can have different address translation
configured then the RTOS support can use this to do the right thing.
Use this in hwthread, where of course address translation can be set up
differently for different real cores.
Change-Id: I62c501cff1f863d855ee197dee7b73204ea8885a
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/6327
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'ChangeLog')
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