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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2020-08-11 14:06:04 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-09-20 14:35:44 +0100 |
| commit | f2c83fade3ea7e51e5c9283aa3ff94632a41cc55 (patch) | |
| tree | a41baefd6013639fb08ce696ccac2f466a7f903f | |
| parent | 6e339478999bab6ae029a3b24fa79ddc698e1a4f (diff) | |
| download | riscv-openocd-f2c83fade3ea7e51e5c9283aa3ff94632a41cc55.zip riscv-openocd-f2c83fade3ea7e51e5c9283aa3ff94632a41cc55.tar.gz riscv-openocd-f2c83fade3ea7e51e5c9283aa3ff94632a41cc55.tar.bz2 | |
cortex_m: read and display core security state
Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/arm.h | 3 | ||||
| -rw-r--r-- | src/target/cortex_m.c | 19 | ||||
| -rw-r--r-- | src/target/cortex_m.h | 4 |
3 files changed, 25 insertions, 1 deletions
diff --git a/src/target/arm.h b/src/target/arm.h index 3450260..d97a95e 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -197,6 +197,9 @@ struct arm { /** Flag reporting armv6m based core. */ bool is_armv6m; + /** Flag reporting armv8m based core. */ + bool is_armv8m; + /** Floating point or VFP version, 0 if disabled. */ int arm_vfp_version; diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 62e0846..4b0ea50 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -502,6 +502,18 @@ static int cortex_m_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; + /* examine PE security state */ + bool secure_state = false; + if (armv7m->arm.is_armv8m) { + uint32_t dscsr; + + retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr); + if (retval != ERROR_OK) + return retval; + + secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS; + } + /* Examine target state and mode * First load register accessible through core debug port */ int num_regs = arm->core_cache->num_regs; @@ -548,9 +560,10 @@ static int cortex_m_debug_entry(struct target *target) if (armv7m->exception_number) cortex_m_examine_exception_reason(target); - LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", + LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s", arm_mode_name(arm->core_mode), buf_get_u32(arm->pc->value, 0, 32), + secure_state ? "Secure" : "Non-Secure", target_state_name(target)); if (armv7m->post_debug_entry) { @@ -2156,6 +2169,9 @@ int cortex_m_examine(struct target *target) /* Get CPU Type */ i = (cpuid >> 4) & 0xf; + /* Check if it is an ARMv8-M core */ + armv7m->arm.is_armv8m = true; + switch (cpuid & ARM_CPUID_PARTNO_MASK) { case CORTEX_M23_PARTNO: i = 23; @@ -2166,6 +2182,7 @@ int cortex_m_examine(struct target *target) break; default: + armv7m->arm.is_armv8m = false; break; } diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 794eda4..3545328 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -50,6 +50,7 @@ #define DCB_DCRSR 0xE000EDF4 #define DCB_DCRDR 0xE000EDF8 #define DCB_DEMCR 0xE000EDFC +#define DCB_DSCSR 0xE000EE08 #define DCRSR_WnR BIT(16) @@ -114,6 +115,9 @@ #define VC_MMERR BIT(4) #define VC_CORERESET BIT(0) +/* DCB_DSCSR bit and field definitions */ +#define DSCSR_CDS BIT(16) + /* NVIC registers */ #define NVIC_ICTR 0xE000E004 #define NVIC_ISE0 0xE000E100 |