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authorAntonio Borneo <borneo.antonio@gmail.com>2024-02-28 13:41:34 +0100
committerAntonio Borneo <borneo.antonio@gmail.com>2024-03-16 14:41:53 +0000
commite9df8a5102106de5a13956759ae52eb72ff68113 (patch)
treee1f57085b4404cfba3f01def5ae3486732222624
parent4c0a2cf42ea0a0b48a948be1ff825629265bbf21 (diff)
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target: aarch64: add support for 32 bit MON mode
Extend the existing code to support Monitor mode in AArch32. Change-Id: Ia43df98d1497baac48aea67b92d81344c24f0635 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8169 Tested-by: jenkins
-rw-r--r--src/target/aarch64.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 36bcddc..2e4d0b5 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -93,6 +93,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -172,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -1043,6 +1045,7 @@ static int aarch64_post_debug_entry(struct target *target)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
break;