Gheorghe Guran <roatlasro@yahoo.com> redone at91sam7 driver. Old driver source file renamed. The old driver is still invoked by default and the new driver is invoked by using at91sam7_new

git-svn-id: svn://svn.berlios.de/openocd/trunk@1007 b42882b7-edfa-0310-969c-e2dbd0fdcd60

7 files changed, 2249 insertions, 912 deletions

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 5bce55f..f9755c75 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -2,8 +2,8 @@ INCLUDES = -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag -I$(top_srcdir)/s
 AM_CPPFLAGS = -DPKGLIBDIR=\"$(pkglibdir)\" @CPPFLAGS@
 METASOURCES = AUTO
 noinst_LIBRARIES = libflash.a
-libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c aduc702x.c nand.c lpc3180_nand_controller.c \
+libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c at91sam7_old.c str7x.c str9x.c aduc702x.c nand.c lpc3180_nand_controller.c \
 					 stellaris.c str9xpec.c stm32x.c tms470.c ecos.c  \
 		     s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c
-noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
+noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h at91sam7_old.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
 				 stellaris.h str9xpec.h stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h
diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index db90d30..3b51c07 100644
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -2,37 +2,39 @@
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
+ *   Copyright (C) 2008 by Gheorghe Guran (atlas)                          *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
+ *   it under the terms of the GNU General public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
  *   (at your option) any later version.                                   *
  *                                                                         *
  *   This program is distributed in the hope that it will be useful,       *
  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
+ *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
+ *   GNU General public License for more details.                          *
  *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
+ *   You should have received a copy of the GNU General public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-
-/***************************************************************************
-There are some things to notice
+****************************************************************************/
 
-* AT91SAM7S64 is tested
-* All AT91SAM7Sxx  and  AT91SAM7Xxx should work but is not tested
-* All parameters are identified from onchip configuartion registers 
+/***************************************************************************************************************************************************************************************
+*
+* New flash setup command:
 *
-* The flash controller handles erases automatically on a page (128/265 byte) basis
-* Only an EraseAll command is supported by the controller
-* Partial erases can be implemented in software by writing one 0xFFFFFFFF word to 
-* some location in every page in the region to be erased
-*  
-* Lock regions (sectors) are 32 or 64 pages
+* flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
 *
- ***************************************************************************/
+*   <ext_freq_khz> - MUST be used if clock is from external source,
+*                    CAN be used if main oscillator frequency is known (recomended)
+* Examples:
+*  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000                   ==== RECOMENDED ============
+*  flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000    (auto-detection, except for clock)      ==== RECOMENDED ============
+*  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0                       ==== NOT RECOMENDED !!! ====
+*  flash bank at91sam7 0 0 0 0 0            (old style, full auto-detection)                    ==== NOT RECOMENDED !!! ====
+****************************************************************************************************************************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -62,893 +64,1150 @@ int at91sam7_erase_check(struct flash_bank_s *bank);
 int at91sam7_protect_check(struct flash_bank_s *bank);
 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
 
-u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane);
-void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
-u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
-int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen); 
+u32 at91sam7_get_flash_status(target_t *target, int bank_number);
+void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
+u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
+int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen); 
 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 flash_driver_t at91sam7_flash =
 {
-	.name = "at91sam7",
-	.register_commands = at91sam7_register_commands,
-	.flash_bank_command = at91sam7_flash_bank_command,
-	.erase = at91sam7_erase,
-	.protect = at91sam7_protect,
-	.write = at91sam7_write,
-	.probe = at91sam7_probe,
-	.auto_probe = at91sam7_probe,
-	.erase_check = at91sam7_erase_check,
-	.protect_check = at91sam7_protect_check,
-	.info = at91sam7_info
+    .name = "at91sam7_new",
+    .register_commands = at91sam7_register_commands,
+    .flash_bank_command = at91sam7_flash_bank_command,
+    .erase = at91sam7_erase,
+    .protect = at91sam7_protect,
+    .write = at91sam7_write,
+    .probe = at91sam7_probe,
+    .auto_probe = at91sam7_probe,
+    .erase_check = at91sam7_erase_check,
+    .protect_check = at91sam7_protect_check,
+    .info = at91sam7_info
 };
 
-u32 MC_FMR[4] =	{ 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
-u32 MC_FCR[4] =	{ 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
-u32 MC_FSR[4] =	{ 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
+
+u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
+u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
+u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
 
 char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
-long NVPSIZ[16] = {
-   0,
-   0x2000, /*  8K */
-   0x4000, /* 16K */ 
-   0x8000, /* 32K */
-   -1,
-   0x10000, /* 64K */
-   -1,
-   0x20000, /* 128K */
-   -1,
-   0x40000, /* 256K */
-   0x80000, /* 512K */
-   -1,
-   0x100000, /* 1024K */
-   -1,
-   0x200000, /* 2048K */
-   -1
-};
 
 long SRAMSIZ[16] = {
-   -1,
-   0x0400, /*  1K */
-   0x0800, /*  2K */ 
-   -1, 
-   0x1c000,  /* 112K */
-   0x1000,  /*   4K */
-   0x14000, /*  80K */
-   0x28000, /* 160K */
-   0x2000,  /*   8K */
-   0x4000,  /*  16K */
-   0x8000,  /*  32K */
-   0x10000, /*  64K */
-   0x20000, /* 128K */
-   0x40000, /* 256K */
-   0x18000, /* 96K */
-   0x80000, /* 512K */
+        -1,
+    0x0400,   /*  1K */
+    0x0800,   /*  2K */ 
+        -1, 
+   0x1c000,   /* 112K */
+    0x1000,   /*   4K */
+   0x14000,   /*  80K */
+   0x28000,   /* 160K */
+    0x2000,   /*   8K */
+    0x4000,   /*  16K */
+    0x8000,   /*  32K */
+   0x10000,   /*  64K */
+   0x20000,   /* 128K */
+   0x40000,   /* 256K */
+   0x18000,   /*  96K */
+   0x80000,   /* 512K */
 };
 
 int at91sam7_register_commands(struct command_context_s *cmd_ctx)
 {
-	command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
-	register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
-			"at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");
+    command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7_new", NULL, COMMAND_ANY, NULL);
 
-	return ERROR_OK;
+    register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
+                     "at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit");
+    return ERROR_OK;
 }
 
-u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane)
+u32 at91sam7_get_flash_status(target_t *target, int bank_number)
 {
-	target_t *target = bank->target;
-	u32 fsr;
-	
-	target_read_u32(target, MC_FSR[flashplane], &fsr);
-	
-	return fsr;
+    u32 fsr;
+    target_read_u32(target, MC_FSR[bank_number], &fsr);
+
+    return fsr;
 }
 
-/* Read clock configuration and set at91sam7_info->usec_clocks*/
+/* Read clock configuration and set at91sam7_info->mck_freq */
 void at91sam7_read_clock_info(flash_bank_t *bank)
 {
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	target_t *target = bank->target;
-	u32 mckr, mcfr, pllr;
-	unsigned long tmp = 0, mainfreq;
-	int flashplane;
-
-	/* Read main clock freqency register */
-	target_read_u32(target, CKGR_MCFR, &mcfr);
-	/* Read master clock register */
-	target_read_u32(target, PMC_MCKR, &mckr);
-	/* Read Clock Generator PLL Register  */
-	target_read_u32(target, CKGR_PLLR, &pllr);
-
-	at91sam7_info->mck_valid = 0;
-	switch (mckr & PMC_MCKR_CSS) 
-	{
-		case 0:			/* Slow Clock */
-			at91sam7_info->mck_valid = 1;
-			mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
-			tmp = mainfreq;
-			break;
-		case 1:			/* Main Clock */
-			if (mcfr & CKGR_MCFR_MAINRDY) 
-			{
-				at91sam7_info->mck_valid = 1;
-				mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
-				tmp = mainfreq;
-			}
-			break;
-
-		case 2:			/* Reserved */
-			break;
-		case 3:			/* PLL Clock */
-			if (mcfr & CKGR_MCFR_MAINRDY) 
-			{
-				target_read_u32(target, CKGR_PLLR, &pllr);
-				if (!(pllr & CKGR_PLLR_DIV))
-					break; /* 0 Hz */
-				at91sam7_info->mck_valid = 1;
-				mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
-				/* Integer arithmetic should have sufficient precision
-				   as long as PLL is properly configured. */
-				tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *
-				  (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
-			}
-			break;
-	}
-	
-	/* Prescaler adjust */
-	if (((mckr & PMC_MCKR_PRES) >> 2) == 7)
-		at91sam7_info->mck_valid = 0;
-	else
-		at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
-
-	/* Forget old flash timing */
-	for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++)
-	{
-		at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE);
-	}
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    target_t *target = bank->target;
+    u32 mckr, mcfr, pllr, mor;
+    unsigned long tmp = 0, mainfreq;
+
+    /* Read Clock Generator Main Oscillator Register */
+    target_read_u32(target, CKGR_MOR, &mor);
+    /* Read Clock Generator Main Clock Frequency Register */
+    target_read_u32(target, CKGR_MCFR, &mcfr);
+    /* Read Master Clock Register*/
+    target_read_u32(target, PMC_MCKR, &mckr);
+    /* Read Clock Generator PLL Register  */
+    target_read_u32(target, CKGR_PLLR, &pllr);
+
+    at91sam7_info->mck_valid = 0;
+    at91sam7_info->mck_freq = 0;
+    switch (mckr & PMC_MCKR_CSS) 
+    {
+        case 0:         /* Slow Clock */
+            at91sam7_info->mck_valid = 1;
+            tmp = RC_FREQ;
+            break;
+
+        case 1:         /* Main Clock */
+            if ((mcfr & CKGR_MCFR_MAINRDY) && 
+                (at91sam7_info->ext_freq == 0))
+            {
+                at91sam7_info->mck_valid = 1;
+                tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
+            }
+            else if (at91sam7_info->ext_freq != 0)
+            {
+                at91sam7_info->mck_valid = 1;
+                tmp = at91sam7_info->ext_freq;
+            }
+            break;
+
+        case 2:         /* Reserved */
+            break;
+
+        case 3:         /* PLL Clock */
+            if ((mcfr & CKGR_MCFR_MAINRDY) && 
+                (at91sam7_info->ext_freq == 0)) 
+            {
+                target_read_u32(target, CKGR_PLLR, &pllr);
+                if (!(pllr & CKGR_PLLR_DIV))
+                    break; /* 0 Hz */
+                at91sam7_info->mck_valid = 1;
+                mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
+                /* Integer arithmetic should have sufficient precision
+                   as long as PLL is properly configured. */
+                tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
+                     (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
+            }
+            else if ((at91sam7_info->ext_freq != 0) &&
+                    ((pllr&CKGR_PLLR_DIV) != 0))
+            {
+                at91sam7_info->mck_valid = 1;
+                tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
+                                 (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
+            }
+            break;
+    }
+
+    /* Prescaler adjust */
+    if ( (((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0) )
+    {
+        at91sam7_info->mck_valid = 0;
+        at91sam7_info->mck_freq = 0;
+    }
+    else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
+        at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
+    else
+        at91sam7_info->mck_freq = tmp;
 }
 
 /* Setup the timimg registers for nvbits or normal flash */
-void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
+void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
 {
-	u32 fmr, fmcn = 0, fws = 0;
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	target_t *target = bank->target;
-	
-	if (mode && (mode != at91sam7_info->flashmode[flashplane]))
-	{
-		/* Always round up (ceil) */
-		if (mode==FMR_TIMING_NVBITS)
-		{
-			if (at91sam7_info->cidr_arch == 0x60)
-			{
-				/* AT91SAM7A3 uses master clocks in 100 ns */
-				fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
-			}
-			else
-			{
-				/* master clocks in 1uS for ARCH 0x7 types */
-				fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
-			}
-		}
-		else if (mode==FMR_TIMING_FLASH)
-			/* main clocks in 1.5uS */
-			fmcn = (at91sam7_info->mck_freq/666666ul)+1;
-
-		/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
- 		if (at91sam7_info->mck_freq <= 33333ul)
-			fmcn = 0;
-		/* Only allow fws=0 if clock frequency is < 30 MHz. */
-		if (at91sam7_info->mck_freq > 30000000ul)
-			fws = 1;
-
-		LOG_DEBUG("fmcn[%i]: %i", flashplane, fmcn); 
-		fmr = fmcn << 16 | fws << 8;
-		target_write_u32(target, MC_FMR[flashplane], fmr);
-	}
-	
-	at91sam7_info->flashmode[flashplane] = mode;		
+    u32 fmr, fmcn = 0, fws = 0;
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    target_t *target = bank->target;
+
+    if (mode && (mode != at91sam7_info->flashmode))
+    {
+        /* Always round up (ceil) */
+        if (mode == FMR_TIMING_NVBITS)
+        {
+            if (at91sam7_info->cidr_arch == 0x60)
+            {
+                /* AT91SAM7A3 uses master clocks in 100 ns */
+                fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
+            }
+            else
+            {
+                /* master clocks in 1uS for ARCH 0x7 types */
+                fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
+            }
+        }
+        else if (mode == FMR_TIMING_FLASH)
+        {
+            /* main clocks in 1.5uS */
+            fmcn = (at91sam7_info->mck_freq/1000000ul)+
+                   (at91sam7_info->mck_freq/2000000ul)+1;
+        }
+
+        /* hard overclocking */
+        if (fmcn > 0xFF)
+            fmcn = 0xFF;
+
+        /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
+        if (at91sam7_info->mck_freq <= 33333ul)
+            fmcn = 0;
+        /* Only allow fws=0 if clock frequency is < 30 MHz. */
+        if (at91sam7_info->mck_freq > 30000000ul)
+            fws = 1;
+
+        LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, fmcn);
+        fmr = fmcn << 16 | fws << 8;
+        target_write_u32(target, MC_FMR[bank->bank_number], fmr);
+    }
+
+    at91sam7_info->flashmode = mode;
 }
 
-u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
+u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
 {
-	u32 status;
-	
-	while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
-	{
-		LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
-		alive_sleep(1);
-	}
-	
-	LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
-
-	if (status & 0x0C)
-	{
-		LOG_ERROR("status register: 0x%x", status);
-		if (status & 0x4)
-			LOG_ERROR("Lock Error Bit Detected, Operation Abort");
-		if (status & 0x8)
-			LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
-		if (status & 0x10)
-			LOG_ERROR("Security Bit Set, Operation Abort");
-	}
-	
-	return status;
+    u32 status;
+
+    while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
+    {
+        LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
+        alive_sleep(1);
+    }
+
+    LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
+
+    if (status & 0x0C)
+    {
+        LOG_ERROR("status register: 0x%x", status);
+        if (status & 0x4)
+            LOG_ERROR("Lock Error Bit Detected, Operation Abort");
+        if (status & 0x8)
+            LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
+        if (status & 0x10)
+            LOG_ERROR("Security Bit Set, Operation Abort");
+    }
+
+    return status;
 }
 
-
 /* Send one command to the AT91SAM flash controller */
-int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen) 
+int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
 {
-	u32 fcr;
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	target_t *target = bank->target;
-
-	fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; 
-	target_write_u32(target, MC_FCR[flashplane], fcr);
-	LOG_DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);
-
-	if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
-	{
-		/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
-		if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C) 
-		{
-			return ERROR_FLASH_OPERATION_FAILED;
-		}
-		return ERROR_OK;
-	}
-
-	if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C) 
-	{
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-	return ERROR_OK;
+    u32 fcr;
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    target_t *target = bank->target;
+
+    fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; 
+    target_write_u32(target, MC_FCR[bank->bank_number], fcr);
+    LOG_DEBUG("Flash command: 0x%x, flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
+
+    if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
+    {
+        /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
+        if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
+        {
+            return ERROR_FLASH_OPERATION_FAILED;
+        }
+        return ERROR_OK;
+    }
+
+    if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C) 
+    {
+        return ERROR_FLASH_OPERATION_FAILED;
+    }
+
+    return ERROR_OK;
 }
 
 /* Read device id register, main clock frequency register and fill in driver info structure */
 int at91sam7_read_part_info(struct flash_bank_s *bank)
 {
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	target_t *target = bank->target;
-	u32 cidr, status;
-	int sectornum;
-
-	if (at91sam7_info->cidr != 0)
-		return ERROR_OK; /* already probed, multiple probes may cause memory leak, not allowed */
-	
-	/* Read and parse chip identification register */
-	target_read_u32(target, DBGU_CIDR, &cidr);
-	
-	if (cidr == 0)
-	{
-		LOG_WARNING("Cannot identify target as an AT91SAM");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-	
-	at91sam7_info->cidr = cidr;
-	at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
-	at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
-	at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
-	at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
-	at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
-	at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
-	at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
-	at91sam7_info->cidr_version = cidr&0x001F;
-	bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz];
-	at91sam7_info->target_name = "Unknown";
-
-	/* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */
-	if (NVPSIZ[at91sam7_info->cidr_nvpsiz]<0x80000)  /* Flash size less than 512K, one flash plane */
-	{
-		bank->num_sectors = 1;
-		bank->sectors = malloc(sizeof(flash_sector_t));
-		bank->sectors[0].offset = 0;
-		bank->sectors[0].size = bank->size;
-		bank->sectors[0].is_erased = -1;
-		bank->sectors[0].is_protected = -1;
-	}
-	else	/* Flash size 512K or larger, several flash planes */
-	{
-		bank->num_sectors = NVPSIZ[at91sam7_info->cidr_nvpsiz]/0x40000;
-		bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t));
-		for (sectornum=0; sectornum<bank->num_sectors; sectornum++)
-		{
-			bank->sectors[sectornum].offset = sectornum*0x40000;
-			bank->sectors[sectornum].size = 0x40000;
-			bank->sectors[sectornum].is_erased = -1;
-			bank->sectors[sectornum].is_protected = -1;
-		}
-	}
-		
-	
-
-	LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
-
-	/* Read main and master clock freqency register */
-	at91sam7_read_clock_info(bank);
-	
-	at91sam7_info->num_planes = 1;
-	status = at91sam7_get_flash_status(bank, 0);
-	at91sam7_info->securitybit = (status>>4)&0x01;
-	at91sam7_protect_check(bank);   /* TODO Check the protect check */
-	
-	if (at91sam7_info->cidr_arch == 0x70 )
-	{
-		at91sam7_info->num_nvmbits = 2;
-		at91sam7_info->nvmbits = (status>>8)&0x03;
-		bank->base = 0x100000;
-		bank->bus_width = 4;
-		if (bank->size==0x80000)  /* AT91SAM7S512 */
-		{
-			at91sam7_info->target_name = "AT91SAM7S512";
-			at91sam7_info->num_planes = 2;
-			if (at91sam7_info->num_planes != bank->num_sectors)
-				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
-			at91sam7_info->num_lockbits = 2*16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 2*16*64;
-		}
-		if (bank->size==0x40000)  /* AT91SAM7S256 */
-		{
-			at91sam7_info->target_name = "AT91SAM7S256";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 16*64;
-		}
-		if (bank->size==0x20000)  /* AT91SAM7S128 */
-		{
-			at91sam7_info->target_name = "AT91SAM7S128";
-			at91sam7_info->num_lockbits = 8;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 8*64;
-		}
-		if (bank->size==0x10000)  /* AT91SAM7S64 */
-		{
-			at91sam7_info->target_name = "AT91SAM7S64";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 128;
-			at91sam7_info->pages_in_lockregion = 32;
-			at91sam7_info->num_pages = 16*32;
-		}
-		if (bank->size==0x08000)  /* AT91SAM7S321/32 */
-		{
-			at91sam7_info->target_name = "AT91SAM7S321/32";
-			at91sam7_info->num_lockbits = 8;
-			at91sam7_info->pagesize = 128;
-			at91sam7_info->pages_in_lockregion = 32;
-			at91sam7_info->num_pages = 8*32;
-		}
-		
-		return ERROR_OK;
-	}
-
-	if (at91sam7_info->cidr_arch == 0x71 )
-	{
-		at91sam7_info->num_nvmbits = 3;
-		at91sam7_info->nvmbits = (status>>8)&0x07;
-		bank->base = 0x100000;
-		bank->bus_width = 4;
-		if (bank->size==0x80000)  /* AT91SAM7XC512 */
-		{
-			at91sam7_info->target_name = "AT91SAM7XC512";
-			at91sam7_info->num_planes = 2;
-			if (at91sam7_info->num_planes != bank->num_sectors)
-				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
-			at91sam7_info->num_lockbits = 2*16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 2*16*64;
-		}
-		if (bank->size==0x40000)  /* AT91SAM7XC256 */
-		{
-			at91sam7_info->target_name = "AT91SAM7XC256";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 16*64;
-		}
-		if (bank->size==0x20000)  /* AT91SAM7XC128 */
-		{
-			at91sam7_info->target_name = "AT91SAM7XC128";
-			at91sam7_info->num_lockbits = 8;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 8*64;
-		}
-		
-		return ERROR_OK;
-	}
-	
-	if (at91sam7_info->cidr_arch == 0x72 )
-	{
-		at91sam7_info->num_nvmbits = 3;
-		at91sam7_info->nvmbits = (status>>8)&0x07;
-		bank->base = 0x100000;
-		bank->bus_width = 4;
-		if (bank->size==0x80000) /* AT91SAM7SE512 */
-		{
-			at91sam7_info->target_name = "AT91SAM7SE512";
-			at91sam7_info->num_planes = 2;
-			if (at91sam7_info->num_planes != bank->num_sectors)
-				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
-			at91sam7_info->num_lockbits = 32;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 32*64;
-		}
-		if (bank->size==0x40000)
-		{
-			at91sam7_info->target_name = "AT91SAM7SE256";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 16*64;
-		}
-		if (bank->size==0x08000)
-		{
-			at91sam7_info->target_name = "AT91SAM7SE32";
-			at91sam7_info->num_lockbits = 8;
-			at91sam7_info->pagesize = 128;
-			at91sam7_info->pages_in_lockregion = 32;
-			at91sam7_info->num_pages = 8*32;
-		}
-		
-		return ERROR_OK;
-	}
-	
-	if (at91sam7_info->cidr_arch == 0x75 )
-	{
-		at91sam7_info->num_nvmbits = 3;
-		at91sam7_info->nvmbits = (status>>8)&0x07;
-		bank->base = 0x100000;
-		bank->bus_width = 4;
-		if (bank->size==0x80000)  /* AT91SAM7X512 */
-		{
-			at91sam7_info->target_name = "AT91SAM7X512";
-			at91sam7_info->num_planes = 2;
-			if (at91sam7_info->num_planes != bank->num_sectors)
-				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
-			at91sam7_info->num_lockbits = 32;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 2*16*64;
-			LOG_DEBUG("Support for AT91SAM7X512 is experimental in this version!");
-		}
-		if (bank->size==0x40000)  /* AT91SAM7X256 */
-		{
-			at91sam7_info->target_name = "AT91SAM7X256";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 16*64;
-		}
-		if (bank->size==0x20000)  /* AT91SAM7X128 */
-		{
-			at91sam7_info->target_name = "AT91SAM7X128";
-			at91sam7_info->num_lockbits = 8;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 64;
-			at91sam7_info->num_pages = 8*64;
-		}
-	
-		return ERROR_OK;
-	}
-	
-	if (at91sam7_info->cidr_arch == 0x60 )
-	{
-		at91sam7_info->num_nvmbits = 3;
-		at91sam7_info->nvmbits = (status>>8)&0x07;
-		bank->base = 0x100000;
-		bank->bus_width = 4;
-		
-		if (bank->size == 0x40000)  /* AT91SAM7A3 */
-		{
-			at91sam7_info->target_name = "AT91SAM7A3";
-			at91sam7_info->num_lockbits = 16;
-			at91sam7_info->pagesize = 256;
-			at91sam7_info->pages_in_lockregion = 16;
-			at91sam7_info->num_pages = 16*64;
-		}
-		return ERROR_OK;
-	}
-	
-	LOG_WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
-	return ERROR_OK;
+    flash_bank_t *t_bank = bank;
+    at91sam7_flash_bank_t *at91sam7_info;
+    target_t *target = t_bank->target;
+
+    u16 bnk, sec;
+    u16 arch;
+    u32 cidr, status;
+    u8 banks_num;
+    u16 num_nvmbits;
+    u16 sectors_num;
+    u16 pages_per_sector;
+    u16 page_size;
+    u32 ext_freq;
+    u32 bank_size;
+    u32 base_address = 0;
+    char *target_name = "Unknown";
+
+    at91sam7_info = t_bank->driver_priv;
+
+    if (at91sam7_info->cidr != 0)
+    {
+        /* flash already configured, update clock and check for protected sectors */
+        flash_bank_t *fb = bank;
+        t_bank = fb;
+
+        while (t_bank)
+        {
+            /* re-calculate master clock frequency */
+            at91sam7_read_clock_info(t_bank);
+
+            /* no timming */
+            at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
+
+            /* check protect state */
+            at91sam7_protect_check(t_bank);
+
+            t_bank = fb->next;
+            fb = t_bank;
+        }
+
+        return ERROR_OK;
+    }
+
+    /* Read and parse chip identification register */
+    target_read_u32(target, DBGU_CIDR, &cidr);
+    if (cidr == 0)
+    {
+        LOG_WARNING("Cannot identify target as an AT91SAM");
+        return ERROR_FLASH_OPERATION_FAILED;
+    }
+
+    if (at91sam7_info->flash_autodetection == 0)
+    {
+        /* banks and sectors are already created, based on data from input file */
+        flash_bank_t *fb = bank;
+        t_bank = fb;
+        while (t_bank)
+        {
+            at91sam7_info = t_bank->driver_priv;
+
+            at91sam7_info->cidr = cidr;
+            at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
+            at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
+            at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
+            at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
+            at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
+            at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
+            at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
+            at91sam7_info->cidr_version = cidr&0x001F;
+
+            /* calculate master clock frequency */
+            at91sam7_read_clock_info(t_bank);
+
+            /* no timming */
+            at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
+
+            /* check protect state */
+            at91sam7_protect_check(t_bank);
+
+            t_bank = fb->next;
+            fb = t_bank;
+        }
+
+        return ERROR_OK;
+    }
+
+    arch = (cidr>>20)&0x00FF;
+
+    /* check flash size */
+    switch ((cidr>>8)&0x000F)
+    {
+        case FLASH_SIZE_8KB:
+            break;
+
+        case FLASH_SIZE_16KB:
+            banks_num = 1;
+            sectors_num = 8;
+            pages_per_sector = 32;
+            page_size  = 64;
+            base_address = 0x00100000;
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S161/16";
+            }
+            break;
+
+        case FLASH_SIZE_32KB:
+            banks_num = 1;
+            sectors_num = 8;
+            pages_per_sector = 32;
+            page_size  = 128;
+            base_address = 0x00100000;
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S321/32";
+            }
+            if (arch == 0x72)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7SE32";
+            }
+            break;
+
+        case FLASH_SIZE_64KB:
+            banks_num = 1;
+            sectors_num = 16;
+            pages_per_sector = 32;
+            page_size  = 128;
+            base_address = 0x00100000;
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S64";
+            }
+            break;
+
+        case FLASH_SIZE_128KB:
+            banks_num = 1;
+            sectors_num = 8;
+            pages_per_sector = 64;
+            page_size  = 256;
+            base_address = 0x00100000;
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S128";
+            }
+            if (arch == 0x71)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7XC128";
+            }
+            if (arch == 0x72)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7SE128";
+            }
+            if (arch == 0x75)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7X128";
+            }
+            break;
+
+        case FLASH_SIZE_256KB:
+            banks_num = 1;
+            sectors_num = 16;
+            pages_per_sector = 64;
+            page_size  = 256;
+            base_address = 0x00100000;
+            if (arch == 0x60)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7A3";
+            }           
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S256";
+            }
+            if (arch == 0x71)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7XC256";
+            }
+            if (arch == 0x72)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7SE256";
+            }
+            if (arch == 0x75)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7X256";
+            }
+            break;
+
+        case FLASH_SIZE_512KB:
+            banks_num = 2;
+            sectors_num = 16;
+            pages_per_sector = 64;
+            page_size  = 256;
+            base_address = 0x00100000;
+            if (arch == 0x70)
+            {
+                num_nvmbits = 2;
+                target_name = "AT91SAM7S512";
+            }
+            if (arch == 0x71)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7XC512";
+            }
+            if (arch == 0x72)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7SE512";
+            }
+            if (arch == 0x75)
+            {
+                num_nvmbits = 3;
+                target_name = "AT91SAM7X512";
+            }
+            break;
+
+        case FLASH_SIZE_1024KB:
+            break;
+
+        case FLASH_SIZE_2048KB:
+            break;
+    }
+
+    if (strcmp(target_name, "Unknown") == 0)
+    {
+        LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
+        return ERROR_FLASH_OPERATION_FAILED;
+    }
+
+    ext_freq = at91sam7_info->ext_freq;
+
+    /* calculate bank size  */
+    bank_size = sectors_num * pages_per_sector * page_size;
+
+    for (bnk=0; bnk<banks_num; bnk++)
+    {
+        if (bnk > 0)
+        {
+            /* create a new flash bank element */
+            flash_bank_t *fb = malloc(sizeof(flash_bank_t));
+            fb->target = target;
+            fb->driver = &at91sam7_flash;
+            fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
+            fb->next = NULL;
+
+            /* link created bank in 'flash_banks' list and redirect t_bank */
+            t_bank->next = fb;
+            t_bank = fb;
+        }
+
+        t_bank->bank_number = bnk;
+        t_bank->base = base_address + bnk * bank_size;
+        t_bank->size = bank_size;
+        t_bank->chip_width = 0;
+        t_bank->bus_width = 4;
+        t_bank->num_sectors = sectors_num;
+
+        /* allocate sectors */
+        t_bank->sectors = malloc(sectors_num * sizeof(flash_sector_t));
+        for (sec=0; sec<sectors_num; sec++)
+        {
+            t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
+            t_bank->sectors[sec].size = pages_per_sector * page_size;
+            t_bank->sectors[sec].is_erased = -1;
+            t_bank->sectors[sec].is_protected = -1;
+        }
+
+        at91sam7_info = t_bank->driver_priv;
+
+        at91sam7_info->cidr = cidr;
+        at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
+        at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
+        at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
+        at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
+        at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
+        at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
+        at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
+        at91sam7_info->cidr_version = cidr&0x001F;
+
+        at91sam7_info->target_name  = target_name;
+        at91sam7_info->flashmode = 0;
+        at91sam7_info->ext_freq = ext_freq;
+        at91sam7_info->num_nvmbits = num_nvmbits;
+        at91sam7_info->num_nvmbits_on = 0;
+        at91sam7_info->pagesize = page_size;
+        at91sam7_info->pages_per_sector = pages_per_sector;
+
+        /* calculate master clock frequency */
+        at91sam7_read_clock_info(t_bank);
+
+        /* no timming */
+        at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
+
+        /* check protect state */       
+        at91sam7_protect_check(t_bank);
+    }
+
+    LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
+
+    return ERROR_OK;
 }
 
 int at91sam7_erase_check(struct flash_bank_s *bank)
 {
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	
-	if (!at91sam7_info->working_area_size)
-	{
-	}
-	else
-	{	
-	}
-	
-	return ERROR_OK;
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+
+    target_t *target = bank->target;
+    u16 retval;
+    u32 blank;
+    u16 fast_check;
+    u8 *buffer;
+    u16 nSector;
+    u16 nByte;
+
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    /* Configure the flash controller timing */
+    at91sam7_read_clock_info(bank); 
+    at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
+
+    fast_check = 1;
+    for (nSector=0; nSector<bank->num_sectors; nSector++)
+    {
+        retval = target_blank_check_memory(target, bank->base+bank->sectors[nSector].offset,
+                                bank->sectors[nSector].size, &blank);
+        if (retval != ERROR_OK)
+        {
+            fast_check = 0;
+            break;
+        }
+        if (blank == 0xFF)
+            bank->sectors[nSector].is_erased = 1;
+        else
+            bank->sectors[nSector].is_erased = 0;
+    }
+
+    if (fast_check)
+    {
+        return ERROR_OK;
+    }
+
+    LOG_USER("Running slow fallback erase check - add working memory");
+    
+    buffer = malloc(bank->sectors[0].size);
+    for (nSector=0; nSector<bank->num_sectors; nSector++)
+    {
+
+        bank->sectors[nSector].is_erased = 1;
+        retval = target->type->read_memory(target, bank->base+bank->sectors[nSector].offset, 4,
+                                           bank->sectors[nSector].size/4, buffer);
+        if (retval != ERROR_OK)
+            return retval;
+
+        for (nByte=0; nByte<bank->sectors[nSector].size; nByte++)
+        {
+            if (buffer[nByte] != 0xFF)
+            {
+                bank->sectors[nSector].is_erased = 0;
+                break;
+            }
+        }
+    }
+    free(buffer);
+
+    return ERROR_OK;
 }
 
 int at91sam7_protect_check(struct flash_bank_s *bank)
 {
-	u32 status;
-	int flashplane;
-	
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-
-	if (at91sam7_info->cidr == 0)
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	for (flashplane=0;flashplane<at91sam7_info->num_planes;flashplane++)
-	{
-		status = at91sam7_get_flash_status(bank, flashplane);
-		at91sam7_info->lockbits[flashplane] = (status >> 16);
-	}
-	
-	return ERROR_OK;
+    u8 lock_pos, gpnvm_pos;
+    u32 status;
+
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+
+    if (at91sam7_info->cidr == 0)
+    {
+        return ERROR_FLASH_BANK_NOT_PROBED;
+    }
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    status = at91sam7_get_flash_status(bank->target, bank->bank_number);
+    at91sam7_info->lockbits = (status>>16);
+
+    at91sam7_info->num_lockbits_on = 0;
+    for (lock_pos=0; lock_pos<bank->num_sectors; lock_pos++)
+    {
+        if ( ((status>>(16+lock_pos))&(0x0001)) == 1)
+        {
+            at91sam7_info->num_lockbits_on++;
+            bank->sectors[lock_pos].is_protected = 1;
+        }
+        else
+            bank->sectors[lock_pos].is_protected = 0;
+    }
+
+    /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
+    status = at91sam7_get_flash_status(bank->target, 0);
+
+    at91sam7_info->securitybit = (status>>4)&0x01;
+    at91sam7_info->nvmbits = (status>>8)&0xFF;
+
+    at91sam7_info->num_nvmbits_on = 0;
+    for (gpnvm_pos=0; gpnvm_pos<at91sam7_info->num_nvmbits; gpnvm_pos++)
+    {
+        if ( ((status>>(8+gpnvm_pos))&(0x01)) == 1)
+        {
+            at91sam7_info->num_nvmbits_on++;
+        }
+    }
+
+    return ERROR_OK;
 }
 
-/* flash_bank at91sam7 0 0 0 0 <target#>
- */
+/***************************************************************************************************************************************************************************************
+# flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+#   <ext_freq_khz> - MUST be used if clock is from external source
+#                    CAN be used if main oscillator frequency is known
+# Examples:
+#  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000                   ==== RECOMENDED ============
+#  flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000    (auto-detection, except for clock)      ==== RECOMENDED ============
+#  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0                       ==== NOT RECOMENDED !!! ====
+#  flash bank at91sam7 0 0 0 0 0                        (old style, full auto-detection)        ==== NOT RECOMENDED !!! ====
+****************************************************************************************************************************************************************************************/
 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 {
-	at91sam7_flash_bank_t *at91sam7_info;
-	int i;
-	
-	if (argc < 6)
-	{
-		LOG_WARNING("incomplete flash_bank at91sam7 configuration");
-		return ERROR_FLASH_BANK_INVALID;
-	}
-	
-	at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));
-	bank->driver_priv = at91sam7_info;
-	
-	/* part wasn't probed for info yet */
-	at91sam7_info->cidr = 0;
-	for (i=0;i<4;i++)
-		at91sam7_info->flashmode[i]=0;
-	
-	return ERROR_OK;
+    flash_bank_t *t_bank = bank;
+    at91sam7_flash_bank_t *at91sam7_info;
+    target_t *target = t_bank->target;
+
+    u32 base_address;
+    u32 bank_size;
+    u32 ext_freq;
+
+    int chip_width;
+    int bus_width;
+    int banks_num;
+    int num_sectors;
+
+    u16 pages_per_sector;
+    u16 page_size;
+    u16 num_nvmbits;
+
+    char *target_name;
+
+    int bnk, sec;
+
+    at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));
+    t_bank->driver_priv = at91sam7_info;
+
+    /* part wasn't probed for info yet */
+    at91sam7_info->cidr = 0;
+    at91sam7_info->flashmode = 0;
+    at91sam7_info->ext_freq = 0;
+    at91sam7_info->flash_autodetection = 0;
+
+    if (argc == 14)
+    {
+        ext_freq = atol(args[13]) * 1000;
+        at91sam7_info->ext_freq = ext_freq;
+    }
+
+    if ((argc != 14)                ||
+        (atoi(args[4]) == 0)        ||  /* bus width */
+        (atoi(args[8]) == 0)        ||  /* banks number */
+        (atoi(args[9]) == 0)        ||  /* sectors per bank */
+        (atoi(args[10]) == 0)       ||  /* pages per sector */
+        (atoi(args[11]) == 0)       ||  /* page size */
+        (atoi(args[12]) == 0))          /* nvmbits number */
+    {
+        at91sam7_info->flash_autodetection = 1;
+        return ERROR_OK;
+    }
+
+    base_address = strtoul(args[1], NULL, 0);
+    chip_width = atoi(args[3]);
+    bus_width = atoi(args[4]);
+    banks_num = atoi(args[8]);
+    num_sectors = atoi(args[9]);
+    pages_per_sector = atoi(args[10]);
+    page_size = atoi(args[11]);
+    num_nvmbits = atoi(args[12]);
+
+    target_name = calloc(strlen(args[7])+1, sizeof(char));
+    strcpy(target_name, args[7]);
+
+    /* calculate bank size  */
+    bank_size = num_sectors * pages_per_sector * page_size;
+
+    for (bnk=0; bnk<banks_num; bnk++)
+    {
+        if (bnk > 0)
+        {
+            /* create a new bank element */
+            flash_bank_t *fb = malloc(sizeof(flash_bank_t));
+            fb->target = target;
+            fb->driver = &at91sam7_flash;
+            fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
+            fb->next = NULL;
+
+            /* link created bank in 'flash_banks' list and redirect t_bank */
+            t_bank->next = fb;
+            t_bank = fb;
+        }
+
+        t_bank->bank_number = bnk;
+        t_bank->base = base_address + bnk * bank_size;
+        t_bank->size = bank_size;
+        t_bank->chip_width = chip_width;
+        t_bank->bus_width = bus_width;
+        t_bank->num_sectors = num_sectors;
+
+        /* allocate sectors */
+        t_bank->sectors = malloc(num_sectors * sizeof(flash_sector_t));
+        for (sec=0; sec<num_sectors; sec++)
+        {
+            t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
+            t_bank->sectors[sec].size = pages_per_sector * page_size;
+            t_bank->sectors[sec].is_erased = -1;
+            t_bank->sectors[sec].is_protected = -1;
+        }
+
+        at91sam7_info = t_bank->driver_priv;
+
+        at91sam7_info->target_name  = target_name;
+        at91sam7_info->flashmode = 0;
+        at91sam7_info->ext_freq  = ext_freq;
+        at91sam7_info->num_nvmbits = num_nvmbits;
+        at91sam7_info->num_nvmbits_on = 0;
+        at91sam7_info->pagesize = page_size;
+        at91sam7_info->pages_per_sector = pages_per_sector;
+    }
+
+    return ERROR_OK;
 }
 
 int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
 {
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	u8 flashplane;
-
-	if (at91sam7_info->cidr == 0)
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-	
-	if ((first < 0) || (last < first) || (last >= bank->num_sectors))
-	{
-		if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))
-		{
-			LOG_WARNING("Sector numbers based on lockbit count, probably a deprecated script");
-			last = bank->num_sectors-1;
-		}
-		else return ERROR_FLASH_SECTOR_INVALID;
-	}
-
-	/* Configure the flash controller timing */
-	at91sam7_read_clock_info(bank);	
-	for (flashplane = first; flashplane<=last; flashplane++)
-	{
-		/* Configure the flash controller timing */
-		at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);
-		if (at91sam7_flash_command(bank, flashplane, EA, 0) != ERROR_OK) 
-		{
-			return ERROR_FLASH_OPERATION_FAILED;
-		}	
-	}
-	return ERROR_OK;
-
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    int sec;
+    u32 nbytes, pos;
+    u8 *buffer;
+    u8 erase_all;
+
+    if (at91sam7_info->cidr == 0)
+    {
+        return ERROR_FLASH_BANK_NOT_PROBED;
+    }
+
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+    {
+        return ERROR_FLASH_SECTOR_INVALID;
+    }
+
+    erase_all = 0;
+    if ((first == 0) && (last == (bank->num_sectors-1)))
+    {
+        erase_all = 1;
+    }
+
+    /* Configure the flash controller timing */
+    at91sam7_read_clock_info(bank);
+    at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
+
+    if(erase_all)
+    {
+        if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK) 
+        {
+            return ERROR_FLASH_OPERATION_FAILED;
+        }
+    }
+    else
+    {
+        /* allocate and clean buffer  */
+        nbytes = (last - first + 1) * bank->sectors[first].size;
+        buffer = malloc(nbytes * sizeof(u8));
+        for (pos=0; pos<nbytes; pos++)
+        {
+             buffer[pos] = 0xFF;
+        }
+
+        if ( at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
+        {
+            return ERROR_FLASH_OPERATION_FAILED;
+        }
+
+        free(buffer);
+    }
+
+    /* mark erased sectors */
+    for (sec=first; sec<=last; sec++)
+    {
+        bank->sectors[sec].is_erased = 1;
+    }
+
+    return ERROR_OK;
 }
 
 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
 {
-	u32 cmd, pagen;
-	u8 flashplane;
-	int lockregion;
-	
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	
-	if (at91sam7_info->cidr == 0)
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-	
-	if ((first < 0) || (last < first) || (last >= at91sam7_info->num_lockbits))
-	{
-		return ERROR_FLASH_SECTOR_INVALID;
-	}
-	
-	at91sam7_read_clock_info(bank);	
-	
-	for (lockregion=first;lockregion<=last;lockregion++) 
-	{
-		pagen = lockregion*at91sam7_info->pages_in_lockregion;
-		flashplane = (pagen>>10)&0x03;
-		/* Configure the flash controller timing */
-		at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NVBITS);
-		
-		if (set)
-			 cmd = SLB; 
-		else
-			 cmd = CLB; 		
-
-		if (at91sam7_flash_command(bank, flashplane, cmd, pagen) != ERROR_OK) 
-		{
-			return ERROR_FLASH_OPERATION_FAILED;
-		}	
-	}
-	
-	at91sam7_protect_check(bank);
-		
-	return ERROR_OK;
+    u32 cmd;
+    u32 sector, pagen;
+
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+
+    if (at91sam7_info->cidr == 0)
+    {
+        return ERROR_FLASH_BANK_NOT_PROBED;
+    }
+
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+    {
+        return ERROR_FLASH_SECTOR_INVALID;
+    }
+
+    /* Configure the flash controller timing */
+    at91sam7_read_clock_info(bank);
+    at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
+
+    for (sector=first; sector<=last; sector++)
+    {
+        if (set)
+             cmd = SLB;
+        else
+             cmd = CLB;
+
+        /* if we lock a page from one sector then entire sector will be locked, also,
+           if we unlock a page from a locked sector, entire sector will be unlocked   */
+        pagen = sector * at91sam7_info->pages_per_sector;
+
+        if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
+        {
+            return ERROR_FLASH_OPERATION_FAILED;
+        }
+    }
+
+    at91sam7_protect_check(bank);
+
+    return ERROR_OK;
 }
 
-
 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 {
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	target_t *target = bank->target;
-	u32 dst_min_alignment, wcount, bytes_remaining = count;
-	u32 first_page, last_page, pagen, buffer_pos;
-	u8 flashplane;
-	
-	if (at91sam7_info->cidr == 0)
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (offset + count > bank->size)
-		return ERROR_FLASH_DST_OUT_OF_BANK;
-	
-	dst_min_alignment = at91sam7_info->pagesize;
-
-	if (offset % dst_min_alignment)
-	{
-		LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
-		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
-	}
-	
-	if (at91sam7_info->cidr_arch == 0)
-		return ERROR_FLASH_BANK_NOT_PROBED;
-
-	first_page = offset/dst_min_alignment;
-	last_page = CEIL(offset + count, dst_min_alignment);
-	
-	LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
-	
-	at91sam7_read_clock_info(bank);	
-
-	for (pagen=first_page; pagen<last_page; pagen++) 
-	{
-		if (bytes_remaining<dst_min_alignment)
-			count = bytes_remaining;
-		else
-			count = dst_min_alignment;
-		bytes_remaining -= count;
-		
-		/* Write one block to the PageWriteBuffer */
-		buffer_pos = (pagen-first_page)*dst_min_alignment;
-		wcount = CEIL(count,4);
-		target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
-		flashplane = (pagen>>10)&0x3;
-		
-		/* Configure the flash controller timing */	
-		at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);
-		/* Send Write Page command to Flash Controller */
-		if (at91sam7_flash_command(bank, flashplane, WP, pagen) != ERROR_OK) 
-		{
-				return ERROR_FLASH_OPERATION_FAILED;
-		}
-		LOG_DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);
-	}
-	
-	return ERROR_OK;
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    target_t *target = bank->target;
+    u32 dst_min_alignment, wcount, bytes_remaining = count;
+    u32 first_page, last_page, pagen, buffer_pos;
+
+    if (at91sam7_info->cidr == 0)
+    {
+        return ERROR_FLASH_BANK_NOT_PROBED;
+    }
+
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    if (offset + count > bank->size)
+        return ERROR_FLASH_DST_OUT_OF_BANK;
+
+    dst_min_alignment = at91sam7_info->pagesize;
+
+    if (offset % dst_min_alignment)
+    {
+        LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
+        return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+    }
+
+    if (at91sam7_info->cidr_arch == 0)
+        return ERROR_FLASH_BANK_NOT_PROBED;
+
+    first_page = offset/dst_min_alignment;
+    last_page = CEIL(offset + count, dst_min_alignment);
+
+    LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
+
+    /* Configure the flash controller timing */
+    at91sam7_read_clock_info(bank);
+    at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
+
+    for (pagen=first_page; pagen<last_page; pagen++)
+    {
+        if (bytes_remaining<dst_min_alignment)
+            count = bytes_remaining;
+        else
+            count = dst_min_alignment;
+        bytes_remaining -= count;
+
+        /* Write one block to the PageWriteBuffer */
+        buffer_pos = (pagen-first_page)*dst_min_alignment;
+        wcount = CEIL(count,4);
+        target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
+
+        /* Send Write Page command to Flash Controller */
+        if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
+        {
+            return ERROR_FLASH_OPERATION_FAILED;
+        }
+        LOG_DEBUG("Write flash bank:%i page number:%i", bank->bank_number, pagen);
+    }
+
+    return ERROR_OK;
 }
 
-
 int at91sam7_probe(struct flash_bank_s *bank)
 {
-	/* we can't probe on an at91sam7
-	 * if this is an at91sam7, it has the configured flash
-	 */
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	int retval;
-	
-	if (at91sam7_info->cidr != 0)
-	{
-		return ERROR_OK; /* already probed */
-	}
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	retval = at91sam7_read_part_info(bank);
-	if (retval != ERROR_OK)
-		return retval;
-	
-	return ERROR_OK;
+    /* we can't probe on an at91sam7
+     * if this is an at91sam7, it has the configured flash
+     */
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+    int retval;
+
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("Target not halted");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    retval = at91sam7_read_part_info(bank);
+    if (retval != ERROR_OK)
+        return retval;
+
+    return ERROR_OK;
 }
 
-
 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
 {
-	int printed, flashplane;
-	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
-	
-	if (at91sam7_info->cidr == 0)
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-	
-	printed = snprintf(buf, buf_size, "\nat91sam7 information: Chip is %s\n",at91sam7_info->target_name);
-	buf += printed;
-	buf_size -= printed;
-	
-	printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x,  flashsize: 0x%8.8x\n",
-		  at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size);
-	buf += printed;
-	buf_size -= printed;
-			
-	printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz \n", at91sam7_info->mck_freq / 1000);
-	buf += printed;
-	buf_size -= printed;
-	
-	if (at91sam7_info->num_planes>1) {		
-		printed = snprintf(buf, buf_size, "flashplanes: %i, pagesize: %i, lock regions: %i, pages in lock region: %i \n", 
-			   at91sam7_info->num_planes, at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->num_pages/at91sam7_info->num_lockbits);
-		buf += printed;
-		buf_size -= printed;
-		for (flashplane=0; flashplane<at91sam7_info->num_planes; flashplane++)
-		{
-			printed = snprintf(buf, buf_size, "lockbits[%i]: 0x%4.4x,  ", flashplane, at91sam7_info->lockbits[flashplane]);
-			buf += printed;
-			buf_size -= printed;
-		}
-	}
-	else
-	if (at91sam7_info->num_lockbits>0) {		
-		printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", 
-			   at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits[0], at91sam7_info->num_pages/at91sam7_info->num_lockbits);
-		buf += printed;
-		buf_size -= printed;
-	}
-			
-	printed = snprintf(buf, buf_size, "securitybit: %i,  nvmbits(%i): 0x%1.1x\n", at91sam7_info->securitybit, at91sam7_info->num_nvmbits, at91sam7_info->nvmbits);
-	buf += printed;
-	buf_size -= printed;
-
-	return ERROR_OK;
+    int printed;
+    at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+
+    if (at91sam7_info->cidr == 0)
+    {
+        return ERROR_FLASH_BANK_NOT_PROBED;
+    }
+
+    printed = snprintf(buf, buf_size,
+            "\n at91sam7 driver information: Chip is %s\n",
+            at91sam7_info->target_name);
+
+    buf += printed;
+    buf_size -= printed;
+
+    printed = snprintf(buf, buf_size,
+            " Cidr: 0x%8.8x | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8x\n",
+            at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc],
+            at91sam7_info->cidr_version, bank->size);
+
+    buf += printed;
+    buf_size -= printed;
+
+    printed = snprintf(buf, buf_size,
+            " Master clock (estimated): %li KHz | External clock: %li KHz\n",
+            at91sam7_info->mck_freq / 1000, at91sam7_info->ext_freq / 1000);
+
+    buf += printed;
+    buf_size -= printed;
+
+    printed = snprintf(buf, buf_size,
+            " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
+            at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
+            at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
+
+    buf += printed;
+    buf_size -= printed;
+
+    printed = snprintf(buf, buf_size,
+            " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
+            at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
+            at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
+
+    buf += printed;
+    buf_size -= printed;
+
+    return ERROR_OK;
 }
 
 /* 
 * On AT91SAM7S: When the gpnvm bits are set with 
-* > at91sam7 gpnvm 0 bitnr set
+* > at91sam7 gpnvm bitnr set
 * the changes are not visible in the flash controller status register MC_FSR 
 * until the processor has been reset.
 * On the Olimex board this requires a power cycle.
 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
-* 	The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
-*	Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
+*   The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
+*   Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
 */
 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
-	flash_bank_t *bank;
-	int bit;
-	u8  flashcmd;
-	u32 status;
-	char *value;
-	at91sam7_flash_bank_t *at91sam7_info;
-	int retval;
-
-	if (argc < 3)
-	{
-		command_print(cmd_ctx, "at91sam7 gpnvm <num> <bit> <set|clear>");
-		return ERROR_OK;
-	}
-	
-	bank = get_flash_bank_by_num_noprobe(strtoul(args[0], NULL, 0));
-	bit = atoi(args[1]);
-	value = args[2];
-
-	if (bank ==  NULL)
-	{
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	if (bank->driver != &at91sam7_flash)
-	{
-		command_print(cmd_ctx, "not an at91sam7 flash bank '%s'", args[0]);
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	if (strcmp(value, "set") == 0)
-	{
-		flashcmd = SGPB;
-	}
-	else if (strcmp(value, "clear") == 0)
-	{
-		flashcmd = CGPB;
-	}
-	else
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	at91sam7_info = bank->driver_priv;
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("target has to be halted to perform flash operation");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-	
-	if (at91sam7_info->cidr == 0)
-	{
-		retval = at91sam7_read_part_info(bank);
-		if (retval != ERROR_OK) {
-			return retval;
-		}
-	}
-
-	if ((bit<0) || (at91sam7_info->num_nvmbits <= bit))
-	{ 
-		command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[1],at91sam7_info->target_name);
-		return ERROR_OK;
-	}
-
-	/* Configure the flash controller timing */
-	at91sam7_read_clock_info(bank);	
-	at91sam7_set_flash_mode(bank, 0, FMR_TIMING_NVBITS);
-	
-	if (at91sam7_flash_command(bank, 0, flashcmd, (u16)(bit)) != ERROR_OK) 
-	{
-		return ERROR_FLASH_OPERATION_FAILED;
-	}	
-
-	status = at91sam7_get_flash_status(bank, 0);
-	LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);
-	at91sam7_info->nvmbits = (status>>8)&((1<<at91sam7_info->num_nvmbits)-1);
-
-	return ERROR_OK;
+    flash_bank_t *bank;
+    int bit;
+    u8  flashcmd;
+    u32 status;
+    at91sam7_flash_bank_t *at91sam7_info;
+    int retval;
+
+    if (argc != 2)
+    {
+        command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set|clear>");
+        return ERROR_OK;
+    }
+
+    bank = get_flash_bank_by_num_noprobe(0);
+    if (bank ==  NULL)
+    {
+        return ERROR_FLASH_BANK_INVALID;
+    }
+    if (bank->driver != &at91sam7_flash)
+    {
+        command_print(cmd_ctx, "not an at91sam7 flash bank '%s'", args[0]);
+        return ERROR_FLASH_BANK_INVALID;
+    }
+    if (bank->target->state != TARGET_HALTED)
+    {
+        LOG_ERROR("target has to be halted to perform flash operation");
+        return ERROR_TARGET_NOT_HALTED;
+    }
+
+    if (strcmp(args[1], "set") == 0)
+    {
+        flashcmd = SGPB;
+    }
+    else if (strcmp(args[1], "clear") == 0)
+    {
+        flashcmd = CGPB;
+    }
+    else
+    {
+        return ERROR_COMMAND_SYNTAX_ERROR;
+    }
+
+    at91sam7_info = bank->driver_priv;
+    if (at91sam7_info->cidr == 0)
+    {
+        retval = at91sam7_read_part_info(bank);
+        if (retval != ERROR_OK)
+        {
+            return retval;
+        }
+    }
+
+    bit = atoi(args[0]);
+    if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
+    {
+        command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[0], at91sam7_info->target_name);
+        return ERROR_OK;
+    }
+
+    /* Configure the flash controller timing */
+    at91sam7_read_clock_info(bank);
+    at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
+
+    if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
+    {
+        return ERROR_FLASH_OPERATION_FAILED;
+    }
+
+    /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
+    status = at91sam7_get_flash_status(bank->target, 0);
+    LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n", flashcmd, bit, status);
+
+    /* check protect state */
+    at91sam7_protect_check(bank);
+
+    return ERROR_OK;
 }
diff --git a/src/flash/at91sam7.h b/src/flash/at91sam7.h
index ecb5670..efc669e 100644
--- a/src/flash/at91sam7.h
+++ b/src/flash/at91sam7.h
@@ -2,6 +2,8 @@
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
+ *   Copyright (C) 2006 by Gheorghe Guran (atlas)                          *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -17,82 +19,102 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef AT91SAM7_H
 #define AT91SAM7_H
 
 #include "flash.h"
 #include "target.h"
 
+
 typedef struct at91sam7_flash_bank_s
 {
-	u32 working_area;
-	u32 working_area_size;
-
-	/* chip id register */
-	u32 cidr;
-	u16 cidr_ext;
-	u16 cidr_nvptyp;
-	u16 cidr_arch;
-	u16 cidr_sramsiz;
-	u16 cidr_nvpsiz;
-	u16 cidr_nvpsiz2;
-	u16 cidr_eproc;
-	u16 cidr_version;
-	char * target_name;
-
-	/* flash geometry */
-	u16 num_pages;
-	u16 pagesize;
-	u16 pages_in_lockregion;
-	u8 num_erase_regions;
-	u8 num_planes;
-	u32 *erase_region_info;
-
-	/* nv memory bits */
-	u16 num_lockbits;
-	u16 lockbits[4];
-	u16 num_nvmbits;
-	u16 nvmbits;
-	u8  securitybit;
-	u8  flashmode[4];         /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */
-
-	/* main clock status */
-	u8  mck_valid;
-	u32 mck_freq;
+    /* chip id register */
+    u32 cidr;
+    u16 cidr_ext;
+    u16 cidr_nvptyp;
+    u16 cidr_arch;
+    u16 cidr_sramsiz;
+    u16 cidr_nvpsiz;
+    u16 cidr_nvpsiz2;
+    u16 cidr_eproc;
+    u16 cidr_version;
+    char *target_name;
+
+    /* flash auto-detection */
+    u8  flash_autodetection;
+
+    /* flash geometry */
+    u16 pages_per_sector;
+    u16 pagesize;
+    u16 pages_in_lockregion;
+
+    /* nv memory bits */
+    u16 num_lockbits_on;
+    u16 lockbits;
+    u16 num_nvmbits;
+    u16 num_nvmbits_on;
+    u16 nvmbits;
+    u8  securitybit;
+
+    /* 0: not init
+       1: fmcn for nvbits (1uS)
+       2: fmcn for flash (1.5uS) */
+    u8  flashmode;
+
+    /* main clock status */
+    u8  mck_valid;
+    u32 mck_freq;
+
+    /* external clock frequency */
+    u32 ext_freq;
 
 } at91sam7_flash_bank_t;
 
+
 /* AT91SAM7 control registers */
-#define DBGU_CIDR 0xFFFFF240
-#define CKGR_MCFR 0xFFFFFC24
-#define CKGR_MCFR_MAINRDY  0x10000
-#define CKGR_PLLR 0xFFFFFC2c
-#define CKGR_PLLR_DIV 0xff
-#define CKGR_PLLR_MUL 0x07ff0000
-#define PMC_MCKR  0xFFFFFC30
-#define PMC_MCKR_CSS  0x03
-#define PMC_MCKR_PRES 0x1c
+#define DBGU_CIDR           0xFFFFF240
+#define CKGR_MCFR           0xFFFFFC24
+#define CKGR_MOR            0xFFFFFC20
+#define CKGR_MCFR_MAINRDY      0x10000
+#define CKGR_PLLR           0xFFFFFC2c
+#define CKGR_PLLR_DIV             0xff
+#define CKGR_PLLR_MUL       0x07ff0000
+#define PMC_MCKR            0xFFFFFC30
+#define PMC_MCKR_CSS              0x03
+#define PMC_MCKR_PRES             0x1c
 
 /* Flash Controller Commands */
-#define  WP   0x01
-#define  SLB  0x02
-#define  WPL  0x03
-#define  CLB  0x04
-#define  EA   0x08
-#define  SGPB 0x0B
-#define  CGPB 0x0D
-#define  SSB  0x0F
+#define WP      0x01
+#define SLB     0x02
+#define WPL     0x03
+#define CLB     0x04
+#define EA      0x08
+#define SGPB    0x0B
+#define CGPB    0x0D
+#define SSB     0x0F
 
 /* MC_FSR bit definitions */
-#define        MC_FSR_FRDY 1
-#define        MC_FSR_EOL 2
+#define MC_FSR_FRDY         1
+#define MC_FSR_EOL          2
 
 /* AT91SAM7 constants */
-#define RC_FREQ  32000
+#define RC_FREQ         32000
+
+/* Flash timing modes */
+#define FMR_TIMING_NONE     0
+#define FMR_TIMING_NVBITS   1
+#define FMR_TIMING_FLASH    2
 
-/*  FLASH_TIMING_MODES */
-#define  FMR_TIMING_NONE    0
-#define  FMR_TIMING_NVBITS  1
-#define  FMR_TIMING_FLASH   2
+/* Flash size constants */
+#define FLASH_SIZE_8KB      1
+#define FLASH_SIZE_16KB     2
+#define FLASH_SIZE_32KB     3
+#define FLASH_SIZE_64KB     5
+#define FLASH_SIZE_128KB    7
+#define FLASH_SIZE_256KB    9
+#define FLASH_SIZE_512KB    10
+#define FLASH_SIZE_1024KB   12
+#define FLASH_SIZE_2048KB   14
 
 #endif /* AT91SAM7_H */
diff --git a/src/flash/at91sam7_old.c b/src/flash/at91sam7_old.c
new file mode 100644
index 0000000..db14da6
--- /dev/null
+++ b/src/flash/at91sam7_old.c
@@ -0,0 +1,954 @@
+/***************************************************************************

+ *   Copyright (C) 2006 by Magnus Lundin                                   *

+ *   lundin@mlu.mine.nu                                                    *

+ *                                                                         *

+ *   This program is free software; you can redistribute it and/or modify  *

+ *   it under the terms of the GNU General Public License as published by  *

+ *   the Free Software Foundation; either version 2 of the License, or     *

+ *   (at your option) any later version.                                   *

+ *                                                                         *

+ *   This program is distributed in the hope that it will be useful,       *

+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

+ *   GNU General Public License for more details.                          *

+ *                                                                         *

+ *   You should have received a copy of the GNU General Public License     *

+ *   along with this program; if not, write to the                         *

+ *   Free Software Foundation, Inc.,                                       *

+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *

+ ***************************************************************************/

+

+/***************************************************************************

+There are some things to notice

+

+* AT91SAM7S64 is tested

+* All AT91SAM7Sxx  and  AT91SAM7Xxx should work but is not tested

+* All parameters are identified from onchip configuartion registers 

+*

+* The flash controller handles erases automatically on a page (128/265 byte) basis

+* Only an EraseAll command is supported by the controller

+* Partial erases can be implemented in software by writing one 0xFFFFFFFF word to 

+* some location in every page in the region to be erased

+*  

+* Lock regions (sectors) are 32 or 64 pages

+*

+ ***************************************************************************/

+#ifdef HAVE_CONFIG_H

+#include "config.h"

+#endif

+

+#include "replacements.h"

+

+#include "at91sam7_old.h"

+

+#include "flash.h"

+#include "target.h"

+#include "log.h"

+#include "binarybuffer.h"

+#include "types.h"

+

+#include <stdlib.h>

+#include <string.h>

+#include <unistd.h>

+

+int at91sam7_old_register_commands(struct command_context_s *cmd_ctx);

+int at91sam7_old_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);

+int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last);

+int at91sam7_old_protect(struct flash_bank_s *bank, int set, int first, int last);

+int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);

+int at91sam7_old_probe(struct flash_bank_s *bank);

+int at91sam7_old_auto_probe(struct flash_bank_s *bank);

+int at91sam7_old_erase_check(struct flash_bank_s *bank);

+int at91sam7_old_protect_check(struct flash_bank_s *bank);

+int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size);

+

+u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane);

+void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);

+u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);

+int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen); 

+int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

+

+flash_driver_t at91sam7_old_flash =

+{

+	.name = "at91sam7",

+	.register_commands = at91sam7_old_register_commands,

+	.flash_bank_command = at91sam7_old_flash_bank_command,

+	.erase = at91sam7_old_erase,

+	.protect = at91sam7_old_protect,

+	.write = at91sam7_old_write,

+	.probe = at91sam7_old_probe,

+	.auto_probe = at91sam7_old_probe,

+	.erase_check = at91sam7_old_erase_check,

+	.protect_check = at91sam7_old_protect_check,

+	.info = at91sam7_old_info

+};

+

+u32 MC_FMR_old[4] =	{ 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };

+u32 MC_FCR_old[4] =	{ 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };

+u32 MC_FSR_old[4] =	{ 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };

+

+char * EPROC_old[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};

+long NVPSIZ_old[16] = {

+   0,

+   0x2000, /*  8K */

+   0x4000, /* 16K */ 

+   0x8000, /* 32K */

+   -1,

+   0x10000, /* 64K */

+   -1,

+   0x20000, /* 128K */

+   -1,

+   0x40000, /* 256K */

+   0x80000, /* 512K */

+   -1,

+   0x100000, /* 1024K */

+   -1,

+   0x200000, /* 2048K */

+   -1

+};

+

+long SRAMSIZ_old[16] = {

+   -1,

+   0x0400, /*  1K */

+   0x0800, /*  2K */ 

+   -1, 

+   0x1c000,  /* 112K */

+   0x1000,  /*   4K */

+   0x14000, /*  80K */

+   0x28000, /* 160K */

+   0x2000,  /*   8K */

+   0x4000,  /*  16K */

+   0x8000,  /*  32K */

+   0x10000, /*  64K */

+   0x20000, /* 128K */

+   0x40000, /* 256K */

+   0x18000, /* 96K */

+   0x80000, /* 512K */

+};

+

+int at91sam7_old_register_commands(struct command_context_s *cmd_ctx)

+{

+	command_t *at91sam7_old_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);

+	register_command(cmd_ctx, at91sam7_old_cmd, "gpnvm", at91sam7_old_handle_gpnvm_command, COMMAND_EXEC,

+			"at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");

+

+	return ERROR_OK;

+}

+

+u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane)

+{

+	target_t *target = bank->target;

+	u32 fsr;

+	

+	target_read_u32(target, MC_FSR_old[flashplane], &fsr);

+	

+	return fsr;

+}

+

+/* Read clock configuration and set at91sam7_old_info->usec_clocks*/

+void at91sam7_old_read_clock_info(flash_bank_t *bank)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	target_t *target = bank->target;

+	u32 mckr, mcfr, pllr;

+	unsigned long tmp = 0, mainfreq;

+	int flashplane;

+

+	/* Read main clock freqency register */

+	target_read_u32(target, CKGR_MCFR_old, &mcfr);

+	/* Read master clock register */

+	target_read_u32(target, PMC_MCKR_old, &mckr);

+	/* Read Clock Generator PLL Register  */

+	target_read_u32(target, CKGR_PLLR_old, &pllr);

+

+	at91sam7_old_info->mck_valid = 0;

+	switch (mckr & PMC_MCKR_CSS_old) 

+	{

+		case 0:			/* Slow Clock */

+			at91sam7_old_info->mck_valid = 1;

+			mainfreq = RC_FREQ_old / 16ul * (mcfr & 0xffff);

+			tmp = mainfreq;

+			break;

+		case 1:			/* Main Clock */

+			if (mcfr & CKGR_MCFR_MAINRDY_old) 

+			{

+				at91sam7_old_info->mck_valid = 1;

+				mainfreq = RC_FREQ_old / 16ul * (mcfr & 0xffff);

+				tmp = mainfreq;

+			}

+			break;

+

+		case 2:			/* Reserved */

+			break;

+		case 3:			/* PLL Clock */

+			if (mcfr & CKGR_MCFR_MAINRDY_old) 

+			{

+				target_read_u32(target, CKGR_PLLR_old, &pllr);

+				if (!(pllr & CKGR_PLLR_DIV_old))

+					break; /* 0 Hz */

+				at91sam7_old_info->mck_valid = 1;

+				mainfreq = RC_FREQ_old / 16ul * (mcfr & 0xffff);

+				/* Integer arithmetic should have sufficient precision

+				   as long as PLL is properly configured. */

+				tmp = mainfreq / (pllr & CKGR_PLLR_DIV_old) *

+				  (((pllr & CKGR_PLLR_MUL_old) >> 16) + 1);

+			}

+			break;

+	}

+	

+	/* Prescaler adjust */

+	if (((mckr & PMC_MCKR_PRES_old) >> 2) == 7)

+		at91sam7_old_info->mck_valid = 0;

+	else

+		at91sam7_old_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES_old) >> 2);

+

+	/* Forget old flash timing */

+	for (flashplane = 0; flashplane<at91sam7_old_info->num_planes; flashplane++)

+	{

+		at91sam7_old_set_flash_mode(bank, flashplane, FMR_TIMING_NONE_old);

+	}

+}

+

+/* Setup the timimg registers for nvbits or normal flash */

+void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)

+{

+	u32 fmr, fmcn = 0, fws = 0;

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	target_t *target = bank->target;

+	

+	if (mode && (mode != at91sam7_old_info->flashmode[flashplane]))

+	{

+		/* Always round up (ceil) */

+		if (mode==FMR_TIMING_NVBITS_old)

+		{

+			if (at91sam7_old_info->cidr_arch == 0x60)

+			{

+				/* AT91SAM7A3 uses master clocks in 100 ns */

+				fmcn = (at91sam7_old_info->mck_freq/10000000ul)+1;

+			}

+			else

+			{

+				/* master clocks in 1uS for ARCH 0x7 types */

+				fmcn = (at91sam7_old_info->mck_freq/1000000ul)+1;

+			}

+		}

+		else if (mode==FMR_TIMING_FLASH_old)

+			/* main clocks in 1.5uS */

+			fmcn = (at91sam7_old_info->mck_freq/666666ul)+1;

+

+		/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */

+ 		if (at91sam7_old_info->mck_freq <= 33333ul)

+			fmcn = 0;

+		/* Only allow fws=0 if clock frequency is < 30 MHz. */

+		if (at91sam7_old_info->mck_freq > 30000000ul)

+			fws = 1;

+

+		LOG_DEBUG("fmcn[%i]: %i", flashplane, fmcn); 

+		fmr = fmcn << 16 | fws << 8;

+		target_write_u32(target, MC_FMR_old[flashplane], fmr);

+	}

+	

+	at91sam7_old_info->flashmode[flashplane] = mode;		

+}

+

+u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)

+{

+	u32 status;

+	

+	while ((!((status = at91sam7_old_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))

+	{

+		LOG_DEBUG("status[%i]: 0x%x", flashplane, status);

+		alive_sleep(1);

+	}

+	

+	LOG_DEBUG("status[%i]: 0x%x", flashplane, status);

+

+	if (status & 0x0C)

+	{

+		LOG_ERROR("status register: 0x%x", status);

+		if (status & 0x4)

+			LOG_ERROR("Lock Error Bit Detected, Operation Abort");

+		if (status & 0x8)

+			LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");

+		if (status & 0x10)

+			LOG_ERROR("Security Bit Set, Operation Abort");

+	}

+	

+	return status;

+}

+

+

+/* Send one command to the AT91SAM flash controller */

+int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen) 

+{

+	u32 fcr;

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	target_t *target = bank->target;

+

+	fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; 

+	target_write_u32(target, MC_FCR_old[flashplane], fcr);

+	LOG_DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);

+

+	if ((at91sam7_old_info->cidr_arch == 0x60)&&((cmd==SLB_old)|(cmd==CLB_old)))

+	{

+		/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */

+		if (at91sam7_old_wait_status_busy(bank, flashplane, MC_FSR_EOL_old, 10)&0x0C) 

+		{

+			return ERROR_FLASH_OPERATION_FAILED;

+		}

+		return ERROR_OK;

+	}

+

+	if (at91sam7_old_wait_status_busy(bank, flashplane, MC_FSR_FRDY_old, 10)&0x0C) 

+	{

+		return ERROR_FLASH_OPERATION_FAILED;

+	}

+	return ERROR_OK;

+}

+

+/* Read device id register, main clock frequency register and fill in driver info structure */

+int at91sam7_old_read_part_info(struct flash_bank_s *bank)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	target_t *target = bank->target;

+	u32 cidr, status;

+	int sectornum;

+

+	if (at91sam7_old_info->cidr != 0)

+		return ERROR_OK; /* already probed, multiple probes may cause memory leak, not allowed */

+	

+	/* Read and parse chip identification register */

+	target_read_u32(target, DBGU_CIDR_old, &cidr);

+	

+	if (cidr == 0)

+	{

+		LOG_WARNING("Cannot identify target as an AT91SAM");

+		return ERROR_FLASH_OPERATION_FAILED;

+	}

+	

+	at91sam7_old_info->cidr = cidr;

+	at91sam7_old_info->cidr_ext = (cidr>>31)&0x0001;

+	at91sam7_old_info->cidr_nvptyp = (cidr>>28)&0x0007;

+	at91sam7_old_info->cidr_arch = (cidr>>20)&0x00FF;

+	at91sam7_old_info->cidr_sramsiz = (cidr>>16)&0x000F;

+	at91sam7_old_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;

+	at91sam7_old_info->cidr_nvpsiz = (cidr>>8)&0x000F;

+	at91sam7_old_info->cidr_eproc = (cidr>>5)&0x0007;

+	at91sam7_old_info->cidr_version = cidr&0x001F;

+	bank->size = NVPSIZ_old[at91sam7_old_info->cidr_nvpsiz];

+	at91sam7_old_info->target_name = "Unknown";

+

+	/* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */

+	if (NVPSIZ_old[at91sam7_old_info->cidr_nvpsiz]<0x80000)  /* Flash size less than 512K, one flash plane */

+	{

+		bank->num_sectors = 1;

+		bank->sectors = malloc(sizeof(flash_sector_t));

+		bank->sectors[0].offset = 0;

+		bank->sectors[0].size = bank->size;

+		bank->sectors[0].is_erased = -1;

+		bank->sectors[0].is_protected = -1;

+	}

+	else	/* Flash size 512K or larger, several flash planes */

+	{

+		bank->num_sectors = NVPSIZ_old[at91sam7_old_info->cidr_nvpsiz]/0x40000;

+		bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t));

+		for (sectornum=0; sectornum<bank->num_sectors; sectornum++)

+		{

+			bank->sectors[sectornum].offset = sectornum*0x40000;

+			bank->sectors[sectornum].size = 0x40000;

+			bank->sectors[sectornum].is_erased = -1;

+			bank->sectors[sectornum].is_protected = -1;

+		}

+	}

+		

+	

+

+	LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_old_info->cidr_nvptyp, at91sam7_old_info->cidr_arch );

+

+	/* Read main and master clock freqency register */

+	at91sam7_old_read_clock_info(bank);

+	

+	at91sam7_old_info->num_planes = 1;

+	status = at91sam7_old_get_flash_status(bank, 0);

+	at91sam7_old_info->securitybit = (status>>4)&0x01;

+	at91sam7_old_protect_check(bank);   /* TODO Check the protect check */

+	

+	if (at91sam7_old_info->cidr_arch == 0x70 )

+	{

+		at91sam7_old_info->num_nvmbits = 2;

+		at91sam7_old_info->nvmbits = (status>>8)&0x03;

+		bank->base = 0x100000;

+		bank->bus_width = 4;

+		if (bank->size==0x80000)  /* AT91SAM7S512 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7S512";

+			at91sam7_old_info->num_planes = 2;

+			if (at91sam7_old_info->num_planes != bank->num_sectors)

+				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;

+			at91sam7_old_info->num_lockbits = 2*16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 2*16*64;

+		}

+		if (bank->size==0x40000)  /* AT91SAM7S256 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7S256";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 16*64;

+		}

+		if (bank->size==0x20000)  /* AT91SAM7S128 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7S128";

+			at91sam7_old_info->num_lockbits = 8;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 8*64;

+		}

+		if (bank->size==0x10000)  /* AT91SAM7S64 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7S64";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 128;

+			at91sam7_old_info->pages_in_lockregion = 32;

+			at91sam7_old_info->num_pages = 16*32;

+		}

+		if (bank->size==0x08000)  /* AT91SAM7S321/32 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7S321/32";

+			at91sam7_old_info->num_lockbits = 8;

+			at91sam7_old_info->pagesize = 128;

+			at91sam7_old_info->pages_in_lockregion = 32;

+			at91sam7_old_info->num_pages = 8*32;

+		}

+		

+		return ERROR_OK;

+	}

+

+	if (at91sam7_old_info->cidr_arch == 0x71 )

+	{

+		at91sam7_old_info->num_nvmbits = 3;

+		at91sam7_old_info->nvmbits = (status>>8)&0x07;

+		bank->base = 0x100000;

+		bank->bus_width = 4;

+		if (bank->size==0x80000)  /* AT91SAM7XC512 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7XC512";

+			at91sam7_old_info->num_planes = 2;

+			if (at91sam7_old_info->num_planes != bank->num_sectors)

+				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;

+			at91sam7_old_info->num_lockbits = 2*16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 2*16*64;

+		}

+		if (bank->size==0x40000)  /* AT91SAM7XC256 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7XC256";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 16*64;

+		}

+		if (bank->size==0x20000)  /* AT91SAM7XC128 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7XC128";

+			at91sam7_old_info->num_lockbits = 8;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 8*64;

+		}

+		

+		return ERROR_OK;

+	}

+	

+	if (at91sam7_old_info->cidr_arch == 0x72 )

+	{

+		at91sam7_old_info->num_nvmbits = 3;

+		at91sam7_old_info->nvmbits = (status>>8)&0x07;

+		bank->base = 0x100000;

+		bank->bus_width = 4;

+		if (bank->size==0x80000) /* AT91SAM7SE512 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7SE512";

+			at91sam7_old_info->num_planes = 2;

+			if (at91sam7_old_info->num_planes != bank->num_sectors)

+				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;

+			at91sam7_old_info->num_lockbits = 32;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 32*64;

+		}

+		if (bank->size==0x40000)

+		{

+			at91sam7_old_info->target_name = "AT91SAM7SE256";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 16*64;

+		}

+		if (bank->size==0x08000)

+		{

+			at91sam7_old_info->target_name = "AT91SAM7SE32";

+			at91sam7_old_info->num_lockbits = 8;

+			at91sam7_old_info->pagesize = 128;

+			at91sam7_old_info->pages_in_lockregion = 32;

+			at91sam7_old_info->num_pages = 8*32;

+		}

+		

+		return ERROR_OK;

+	}

+	

+	if (at91sam7_old_info->cidr_arch == 0x75 )

+	{

+		at91sam7_old_info->num_nvmbits = 3;

+		at91sam7_old_info->nvmbits = (status>>8)&0x07;

+		bank->base = 0x100000;

+		bank->bus_width = 4;

+		if (bank->size==0x80000)  /* AT91SAM7X512 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7X512";

+			at91sam7_old_info->num_planes = 2;

+			if (at91sam7_old_info->num_planes != bank->num_sectors)

+				LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;

+			at91sam7_old_info->num_lockbits = 32;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 2*16*64;

+			LOG_DEBUG("Support for AT91SAM7X512 is experimental in this version!");

+		}

+		if (bank->size==0x40000)  /* AT91SAM7X256 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7X256";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 16*64;

+		}

+		if (bank->size==0x20000)  /* AT91SAM7X128 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7X128";

+			at91sam7_old_info->num_lockbits = 8;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 64;

+			at91sam7_old_info->num_pages = 8*64;

+		}

+	

+		return ERROR_OK;

+	}

+	

+	if (at91sam7_old_info->cidr_arch == 0x60 )

+	{

+		at91sam7_old_info->num_nvmbits = 3;

+		at91sam7_old_info->nvmbits = (status>>8)&0x07;

+		bank->base = 0x100000;

+		bank->bus_width = 4;

+		

+		if (bank->size == 0x40000)  /* AT91SAM7A3 */

+		{

+			at91sam7_old_info->target_name = "AT91SAM7A3";

+			at91sam7_old_info->num_lockbits = 16;

+			at91sam7_old_info->pagesize = 256;

+			at91sam7_old_info->pages_in_lockregion = 16;

+			at91sam7_old_info->num_pages = 16*64;

+		}

+		return ERROR_OK;

+	}

+	

+	LOG_WARNING("at91sam7_old flash only tested for AT91SAM7Sxx series");

+	return ERROR_OK;

+}

+

+int at91sam7_old_erase_check(struct flash_bank_s *bank)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	

+	if (!at91sam7_old_info->working_area_size)

+	{

+	}

+	else

+	{	

+	}

+	

+	return ERROR_OK;

+}

+

+int at91sam7_old_protect_check(struct flash_bank_s *bank)

+{

+	u32 status;

+	int flashplane;

+	

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+

+	if (at91sam7_old_info->cidr == 0)

+	{

+		return ERROR_FLASH_BANK_NOT_PROBED;

+	}

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("Target not halted");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+

+	for (flashplane=0;flashplane<at91sam7_old_info->num_planes;flashplane++)

+	{

+		status = at91sam7_old_get_flash_status(bank, flashplane);

+		at91sam7_old_info->lockbits[flashplane] = (status >> 16);

+	}

+	

+	return ERROR_OK;

+}

+

+/* flash_bank at91sam7_old 0 0 0 0 <target#>

+ */

+int at91sam7_old_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info;

+	int i;

+	

+	if (argc < 6)

+	{

+		LOG_WARNING("incomplete flash_bank at91sam7_old configuration");

+		return ERROR_FLASH_BANK_INVALID;

+	}

+	

+	at91sam7_old_info = malloc(sizeof(at91sam7_old_flash_bank_t));

+	bank->driver_priv = at91sam7_old_info;

+	

+	/* part wasn't probed for info yet */

+	at91sam7_old_info->cidr = 0;

+	for (i=0;i<4;i++)

+		at91sam7_old_info->flashmode[i]=0;

+	

+	return ERROR_OK;

+}

+

+int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	u8 flashplane;

+

+	if (at91sam7_old_info->cidr == 0)

+	{

+		return ERROR_FLASH_BANK_NOT_PROBED;

+	}

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("Target not halted");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+	

+	if ((first < 0) || (last < first) || (last >= bank->num_sectors))

+	{

+		if ((first == 0) && (last == (at91sam7_old_info->num_lockbits-1)))

+		{

+			LOG_WARNING("Sector numbers based on lockbit count, probably a deprecated script");

+			last = bank->num_sectors-1;

+		}

+		else return ERROR_FLASH_SECTOR_INVALID;

+	}

+

+	/* Configure the flash controller timing */

+	at91sam7_old_read_clock_info(bank);	

+	for (flashplane = first; flashplane<=last; flashplane++)

+	{

+		/* Configure the flash controller timing */

+		at91sam7_old_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH_old);

+		if (at91sam7_old_flash_command(bank, flashplane, EA_old, 0) != ERROR_OK) 

+		{

+			return ERROR_FLASH_OPERATION_FAILED;

+		}	

+	}

+	return ERROR_OK;

+

+}

+

+int at91sam7_old_protect(struct flash_bank_s *bank, int set, int first, int last)

+{

+	u32 cmd, pagen;

+	u8 flashplane;

+	int lockregion;

+	

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	

+	if (at91sam7_old_info->cidr == 0)

+	{

+		return ERROR_FLASH_BANK_NOT_PROBED;

+	}

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("Target not halted");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+	

+	if ((first < 0) || (last < first) || (last >= at91sam7_old_info->num_lockbits))

+	{

+		return ERROR_FLASH_SECTOR_INVALID;

+	}

+	

+	at91sam7_old_read_clock_info(bank);	

+	

+	for (lockregion=first;lockregion<=last;lockregion++) 

+	{

+		pagen = lockregion*at91sam7_old_info->pages_in_lockregion;

+		flashplane = (pagen>>10)&0x03;

+		/* Configure the flash controller timing */

+		at91sam7_old_set_flash_mode(bank, flashplane, FMR_TIMING_NVBITS_old);

+		

+		if (set)

+			 cmd = SLB_old; 

+		else

+			 cmd = CLB_old; 		

+

+		if (at91sam7_old_flash_command(bank, flashplane, cmd, pagen) != ERROR_OK) 

+		{

+			return ERROR_FLASH_OPERATION_FAILED;

+		}	

+	}

+	

+	at91sam7_old_protect_check(bank);

+		

+	return ERROR_OK;

+}

+

+

+int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)

+{

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	target_t *target = bank->target;

+	u32 dst_min_alignment, wcount, bytes_remaining = count;

+	u32 first_page, last_page, pagen, buffer_pos;

+	u8 flashplane;

+	

+	if (at91sam7_old_info->cidr == 0)

+	{

+		return ERROR_FLASH_BANK_NOT_PROBED;

+	}

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("Target not halted");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+

+	if (offset + count > bank->size)

+		return ERROR_FLASH_DST_OUT_OF_BANK;

+	

+	dst_min_alignment = at91sam7_old_info->pagesize;

+

+	if (offset % dst_min_alignment)

+	{

+		LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);

+		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;

+	}

+	

+	if (at91sam7_old_info->cidr_arch == 0)

+		return ERROR_FLASH_BANK_NOT_PROBED;

+

+	first_page = offset/dst_min_alignment;

+	last_page = CEIL(offset + count, dst_min_alignment);

+	

+	LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);

+	

+	at91sam7_old_read_clock_info(bank);	

+

+	for (pagen=first_page; pagen<last_page; pagen++) 

+	{

+		if (bytes_remaining<dst_min_alignment)

+			count = bytes_remaining;

+		else

+			count = dst_min_alignment;

+		bytes_remaining -= count;

+		

+		/* Write one block to the PageWriteBuffer */

+		buffer_pos = (pagen-first_page)*dst_min_alignment;

+		wcount = CEIL(count,4);

+		target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);

+		flashplane = (pagen>>10)&0x3;

+		

+		/* Configure the flash controller timing */	

+		at91sam7_old_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH_old);

+		/* Send Write Page command to Flash Controller */

+		if (at91sam7_old_flash_command(bank, flashplane, WP_old, pagen) != ERROR_OK) 

+		{

+				return ERROR_FLASH_OPERATION_FAILED;

+		}

+		LOG_DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);

+	}

+	

+	return ERROR_OK;

+}

+

+

+int at91sam7_old_probe(struct flash_bank_s *bank)

+{

+	/* we can't probe on an at91sam7_old

+	 * if this is an at91sam7_old, it has the configured flash

+	 */

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	int retval;

+	

+	if (at91sam7_old_info->cidr != 0)

+	{

+		return ERROR_OK; /* already probed */

+	}

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("Target not halted");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+

+	retval = at91sam7_old_read_part_info(bank);

+	if (retval != ERROR_OK)

+		return retval;

+	

+	return ERROR_OK;

+}

+

+

+int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size)

+{

+	int printed, flashplane;

+	at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;

+	

+	if (at91sam7_old_info->cidr == 0)

+	{

+		return ERROR_FLASH_BANK_NOT_PROBED;

+	}

+	

+	printed = snprintf(buf, buf_size, "\nat91sam7_old information: Chip is %s\n",at91sam7_old_info->target_name);

+	buf += printed;

+	buf_size -= printed;

+	

+	printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x,  flashsize: 0x%8.8x\n",

+		  at91sam7_old_info->cidr, at91sam7_old_info->cidr_arch, EPROC_old[at91sam7_old_info->cidr_eproc], at91sam7_old_info->cidr_version, bank->size);

+	buf += printed;

+	buf_size -= printed;

+			

+	printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz \n", at91sam7_old_info->mck_freq / 1000);

+	buf += printed;

+	buf_size -= printed;

+	

+	if (at91sam7_old_info->num_planes>1) {		

+		printed = snprintf(buf, buf_size, "flashplanes: %i, pagesize: %i, lock regions: %i, pages in lock region: %i \n", 

+			   at91sam7_old_info->num_planes, at91sam7_old_info->pagesize, at91sam7_old_info->num_lockbits, at91sam7_old_info->num_pages/at91sam7_old_info->num_lockbits);

+		buf += printed;

+		buf_size -= printed;

+		for (flashplane=0; flashplane<at91sam7_old_info->num_planes; flashplane++)

+		{

+			printed = snprintf(buf, buf_size, "lockbits[%i]: 0x%4.4x,  ", flashplane, at91sam7_old_info->lockbits[flashplane]);

+			buf += printed;

+			buf_size -= printed;

+		}

+	}

+	else

+	if (at91sam7_old_info->num_lockbits>0) {		

+		printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", 

+			   at91sam7_old_info->pagesize, at91sam7_old_info->num_lockbits, at91sam7_old_info->lockbits[0], at91sam7_old_info->num_pages/at91sam7_old_info->num_lockbits);

+		buf += printed;

+		buf_size -= printed;

+	}

+			

+	printed = snprintf(buf, buf_size, "securitybit: %i,  nvmbits(%i): 0x%1.1x\n", at91sam7_old_info->securitybit, at91sam7_old_info->num_nvmbits, at91sam7_old_info->nvmbits);

+	buf += printed;

+	buf_size -= printed;

+

+	return ERROR_OK;

+}

+

+/* 

+* On AT91SAM7S: When the gpnvm bits are set with 

+* > at91sam7_old gpnvm 0 bitnr set

+* the changes are not visible in the flash controller status register MC_FSR_old 

+* until the processor has been reset.

+* On the Olimex board this requires a power cycle.

+* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):

+* 	The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes

+*	Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.

+*/

+int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)

+{

+	flash_bank_t *bank;

+	int bit;

+	u8  flashcmd;

+	u32 status;

+	char *value;

+	at91sam7_old_flash_bank_t *at91sam7_old_info;

+	int retval;

+

+	if (argc < 3)

+	{

+		command_print(cmd_ctx, "at91sam7_old gpnvm <num> <bit> <set|clear>");

+		return ERROR_OK;

+	}

+	

+	bank = get_flash_bank_by_num_noprobe(strtoul(args[0], NULL, 0));

+	bit = atoi(args[1]);

+	value = args[2];

+

+	if (bank ==  NULL)

+	{

+		return ERROR_FLASH_BANK_INVALID;

+	}

+

+	if (bank->driver != &at91sam7_old_flash)

+	{

+		command_print(cmd_ctx, "not an at91sam7_old flash bank '%s'", args[0]);

+		return ERROR_FLASH_BANK_INVALID;

+	}

+

+	if (strcmp(value, "set") == 0)

+	{

+		flashcmd = SGPB_old;

+	}

+	else if (strcmp(value, "clear") == 0)

+	{

+		flashcmd = CGPB_old;

+	}

+	else

+	{

+		return ERROR_COMMAND_SYNTAX_ERROR;

+	}

+

+	at91sam7_old_info = bank->driver_priv;

+

+	if (bank->target->state != TARGET_HALTED)

+	{

+		LOG_ERROR("target has to be halted to perform flash operation");

+		return ERROR_TARGET_NOT_HALTED;

+	}

+	

+	if (at91sam7_old_info->cidr == 0)

+	{

+		retval = at91sam7_old_read_part_info(bank);

+		if (retval != ERROR_OK) {

+			return retval;

+		}

+	}

+

+	if ((bit<0) || (at91sam7_old_info->num_nvmbits <= bit))

+	{ 

+		command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[1],at91sam7_old_info->target_name);

+		return ERROR_OK;

+	}

+

+	/* Configure the flash controller timing */

+	at91sam7_old_read_clock_info(bank);	

+	at91sam7_old_set_flash_mode(bank, 0, FMR_TIMING_NVBITS_old);

+	

+	if (at91sam7_old_flash_command(bank, 0, flashcmd, (u16)(bit)) != ERROR_OK) 

+	{

+		return ERROR_FLASH_OPERATION_FAILED;

+	}	

+

+	status = at91sam7_old_get_flash_status(bank, 0);

+	LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);

+	at91sam7_old_info->nvmbits = (status>>8)&((1<<at91sam7_old_info->num_nvmbits)-1);

+

+	return ERROR_OK;

+}

diff --git a/src/flash/at91sam7_old.h b/src/flash/at91sam7_old.h
new file mode 100644
index 0000000..0850456
--- /dev/null
+++ b/src/flash/at91sam7_old.h
@@ -0,0 +1,98 @@
+/***************************************************************************

+ *   Copyright (C) 2006 by Magnus Lundin                                   *

+ *   lundin@mlu.mine.nu                                                    *

+ *                                                                         *

+ *   This program is free software; you can redistribute it and/or modify  *

+ *   it under the terms of the GNU General Public License as published by  *

+ *   the Free Software Foundation; either version 2 of the License, or     *

+ *   (at your option) any later version.                                   *

+ *                                                                         *

+ *   This program is distributed in the hope that it will be useful,       *

+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *

+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *

+ *   GNU General Public License for more details.                          *

+ *                                                                         *

+ *   You should have received a copy of the GNU General Public License     *

+ *   along with this program; if not, write to the                         *

+ *   Free Software Foundation, Inc.,                                       *

+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *

+ ***************************************************************************/

+#ifndef AT91SAM7_OLD_H

+#define AT91SAM7_OLD_H

+

+#include "flash.h"

+#include "target.h"

+

+typedef struct at91sam7_old_flash_bank_s

+{

+	u32 working_area;

+	u32 working_area_size;

+

+	/* chip id register */

+	u32 cidr;

+	u16 cidr_ext;

+	u16 cidr_nvptyp;

+	u16 cidr_arch;

+	u16 cidr_sramsiz;

+	u16 cidr_nvpsiz;

+	u16 cidr_nvpsiz2;

+	u16 cidr_eproc;

+	u16 cidr_version;

+	char * target_name;

+

+	/* flash geometry */

+	u16 num_pages;

+	u16 pagesize;

+	u16 pages_in_lockregion;

+	u8 num_erase_regions;

+	u8 num_planes;

+	u32 *erase_region_info;

+

+	/* nv memory bits */

+	u16 num_lockbits;

+	u16 lockbits[4];

+	u16 num_nvmbits;

+	u16 nvmbits;

+	u8  securitybit;

+	u8  flashmode[4];         /* 0: not init, 1: fmcn for nvbits (1uS), 2: fmcn for flash (1.5uS) */

+

+	/* main clock status */

+	u8  mck_valid;

+	u32 mck_freq;

+

+} at91sam7_old_flash_bank_t;

+

+/* AT91SAM7 control registers */

+#define DBGU_CIDR_old 0xFFFFF240

+#define CKGR_MCFR_old 0xFFFFFC24

+#define CKGR_MCFR_MAINRDY_old  0x10000

+#define CKGR_PLLR_old 0xFFFFFC2c

+#define CKGR_PLLR_DIV_old 0xff

+#define CKGR_PLLR_MUL_old 0x07ff0000

+#define PMC_MCKR_old  0xFFFFFC30

+#define PMC_MCKR_CSS_old  0x03

+#define PMC_MCKR_PRES_old 0x1c

+

+/* Flash Controller Commands */

+#define  WP_old   0x01

+#define  SLB_old  0x02

+#define  WPL_old  0x03

+#define  CLB_old  0x04

+#define  EA_old   0x08

+#define  SGPB_old 0x0B

+#define  CGPB_old 0x0D

+#define  SSB_old  0x0F

+

+/* MC_FSR bit definitions */

+#define        MC_FSR_FRDY_old 1

+#define        MC_FSR_EOL_old 2

+

+/* AT91SAM7 constants */

+#define RC_FREQ_old  32000

+

+/*  FLASH_TIMING_MODES */

+#define  FMR_TIMING_NONE_old    0

+#define  FMR_TIMING_NVBITS_old  1

+#define  FMR_TIMING_FLASH_old   2

+

+#endif /* AT91SAM7_OLD_H */

diff --git a/src/flash/flash.c b/src/flash/flash.c
index 3d450ac..b2ebe0b 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -67,6 +67,7 @@ flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr);
 extern flash_driver_t lpc2000_flash;
 extern flash_driver_t cfi_flash;
 extern flash_driver_t at91sam7_flash;
+extern flash_driver_t at91sam7_old_flash;
 extern flash_driver_t str7x_flash;
 extern flash_driver_t str9x_flash;
 extern flash_driver_t aduc702x_flash;
@@ -78,24 +79,26 @@ extern flash_driver_t ecosflash_flash;
 extern flash_driver_t lpc288x_flash;
 extern flash_driver_t ocl_flash;
 
-flash_driver_t *flash_drivers[] =
-{
-	&lpc2000_flash,
-	&cfi_flash,
-	&at91sam7_flash,
-	&str7x_flash,
-	&str9x_flash,
-	&aduc702x_flash,
-	&stellaris_flash,
-	&str9xpec_flash,
-	&stm32x_flash,
-	&tms470_flash,
-	&ecosflash_flash,
-	&lpc288x_flash,
-	&ocl_flash,
-	NULL,
+flash_driver_t *flash_drivers[] = {
+        &lpc2000_flash,
+        &cfi_flash,
+        &at91sam7_flash,
+        &at91sam7_old_flash,
+        &str7x_flash,
+        &str9x_flash,
+        &aduc702x_flash,
+        &stellaris_flash,
+        &str9xpec_flash,
+        &stm32x_flash,
+        &tms470_flash,
+        &ecosflash_flash,
+        &lpc288x_flash,
+        &ocl_flash,
+        NULL,
 };
 
+
+
 flash_bank_t *flash_banks;
 static 	command_t *flash_cmd;
 
@@ -379,7 +382,7 @@ int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char
 				else
 					protect_state = "protection state unknown";
 
-				command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%x %ikB) %s",
+				command_print(cmd_ctx, "\t#%3i: 0x%8.8x (0x%x %ikB) %s",
 							j, p->sectors[j].offset, p->sectors[j].size, p->sectors[j].size>>10,
 							protect_state);
 			}
@@ -466,7 +469,7 @@ int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cm
 			else
 				erase_state = "erase state unknown";
 
-			command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%x %ikB) %s",
+			command_print(cmd_ctx, "\t#%3i: 0x%8.8x (0x%x %ikB) %s",
 						j, p->sectors[j].offset, p->sectors[j].size, p->sectors[j].size>>10,
 						erase_state);
 		}
diff --git a/src/flash/flash.h b/src/flash/flash.h
index 904c0c7..4ccbc04 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -68,6 +68,7 @@ typedef struct flash_bank_s
 	target_t *target;
 	flash_driver_t *driver;
 	void *driver_priv;
+	int bank_number;
 	u32 base;
 	u32 size;
 	int chip_width;
@@ -91,13 +92,13 @@ extern flash_bank_t *get_flash_bank_by_num(int num);
 extern flash_bank_t *get_flash_bank_by_num_noprobe(int num);
 extern flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr);
 
-#define		ERROR_FLASH_BANK_INVALID		(-900)
-#define		ERROR_FLASH_SECTOR_INVALID		(-901)
-#define		ERROR_FLASH_OPERATION_FAILED	(-902)
-#define		ERROR_FLASH_DST_OUT_OF_BANK		(-903)
-#define		ERROR_FLASH_DST_BREAKS_ALIGNMENT (-904)
-#define		ERROR_FLASH_BUSY				(-905)
-#define		ERROR_FLASH_SECTOR_NOT_ERASED	(-906)
-#define		ERROR_FLASH_BANK_NOT_PROBED		(-907)
+#define    ERROR_FLASH_BANK_INVALID            (-900)
+#define    ERROR_FLASH_SECTOR_INVALID          (-901)
+#define    ERROR_FLASH_OPERATION_FAILED        (-902)
+#define    ERROR_FLASH_DST_OUT_OF_BANK         (-903)
+#define    ERROR_FLASH_DST_BREAKS_ALIGNMENT    (-904)
+#define    ERROR_FLASH_BUSY                    (-905)
+#define    ERROR_FLASH_SECTOR_NOT_ERASED       (-906)
+#define    ERROR_FLASH_BANK_NOT_PROBED         (-907)
 
 #endif /* FLASH_H */