diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-12-14 09:38:46 +0100 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-05-08 15:21:49 -0700 |
| commit | e1808bad7970513b39f829597cc9bac72ed60f36 (patch) | |
| tree | 311b0aac55ce2f63a5b4878347cbe89f3c49124c | |
| parent | eee2da27ae60f7c0cba216dcbb36789e831029e8 (diff) | |
| download | riscv-openocd-e1808bad7970513b39f829597cc9bac72ed60f36.zip riscv-openocd-e1808bad7970513b39f829597cc9bac72ed60f36.tar.gz riscv-openocd-e1808bad7970513b39f829597cc9bac72ed60f36.tar.bz2 | |
target: add configuration for NXP MC-IMX8M-EVK
includes target configuration for i.MX8M SoC family,
board file needs to set up CHIPNAME and CHIPCORES
to match the actual hardware configuration
Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4434
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
| -rw-r--r-- | tcl/board/nxp_mcimx8m-evk.cfg | 22 | ||||
| -rw-r--r-- | tcl/target/imx8m.cfg | 55 |
2 files changed, 77 insertions, 0 deletions
diff --git a/tcl/board/nxp_mcimx8m-evk.cfg b/tcl/board/nxp_mcimx8m-evk.cfg new file mode 100644 index 0000000..e2d63ce --- /dev/null +++ b/tcl/board/nxp_mcimx8m-evk.cfg @@ -0,0 +1,22 @@ +# +# configuration file for NXP MC-IMX8M-EVK +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter_khz 1000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter_nsrst_delay 70 + +# board has an i.MX8MQ with 4 Cortex-A53 cores +set CHIPNAME imx8mq +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8m.cfg] diff --git a/tcl/target/imx8m.cfg b/tcl/target/imx8m.cfg new file mode 100644 index 0000000..3314954 --- /dev/null +++ b/tcl/target/imx8m.cfg @@ -0,0 +1,55 @@ +# +# configuration file for NXP i.MX8M family of SoCs +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8m +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# the DAP tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -ctibase [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + set _smp_command "target smp $_TARGETNAME.$_core" + } + + eval $_command +} + +eval $_smp_command +targets $_TARGETNAME.0 |