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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 05:14:32 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 05:14:32 +0000 |
commit | 76b78feef1f0181bbcc388f21d185d0b4fa83cfb (patch) | |
tree | 40fe83b0a99b7083d59509332623eb95ede0adaa | |
parent | a89dd2ca6542d157890656d918d6ae2f933ab401 (diff) | |
download | riscv-openocd-76b78feef1f0181bbcc388f21d185d0b4fa83cfb.zip riscv-openocd-76b78feef1f0181bbcc388f21d185d0b4fa83cfb.tar.gz riscv-openocd-76b78feef1f0181bbcc388f21d185d0b4fa83cfb.tar.bz2 |
David Claffey <dnclaffey@gmail.com> get rid of reset recursion
git-svn-id: svn://svn.berlios.de/openocd/trunk@2664 b42882b7-edfa-0310-969c-e2dbd0fdcd60
-rw-r--r-- | tcl/target/ar71xx.cfg | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index f2f5289..213048a 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -13,16 +13,17 @@ jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 set TARGETNAME [format "%s.cpu" $CHIPNAME] target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME -$TARGETNAME configure -event reset-init { +$TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0 mww 0xb8050000 0x800f40a3 # send to PLL #next command will reset for PLL changes to take effect mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC) - reset halt # let openocd know that it is in the reset state +} - #initialize_pll +$TARGETNAME configure -event reset-init { + #complete pll initialization mww 0xb8050000 0x800f0080 # set sw_update bit mww 0xb8050008 0 # clear reset_switch bit mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass |