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| author | Juha Niskanen <juha.niskanen@haltian.com> | 2017-05-04 13:43:08 +0300 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2017-05-08 18:07:41 +0100 |
| commit | 753cf12700959d05fd4e000cbd9951c22c5a2bfa (patch) | |
| tree | c885d7777a86b210b79f8a65f7922ab96d517c03 | |
| parent | f22b89d9fbc0d44b23f56e71429d0df909430036 (diff) | |
| download | riscv-openocd-753cf12700959d05fd4e000cbd9951c22c5a2bfa.zip riscv-openocd-753cf12700959d05fd4e000cbd9951c22c5a2bfa.tar.gz riscv-openocd-753cf12700959d05fd4e000cbd9951c22c5a2bfa.tar.bz2 | |
stm32l4: support flashing L45x/46x devices
Also fixes incorrect comment about MSI range.
Change-Id: If1339a00e50db44195dfcd5c767ba3f5d9035451
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Reviewed-on: http://openocd.zylin.com/4122
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
| -rw-r--r-- | src/flash/nor/stm32l4x.c | 25 | ||||
| -rw-r--r-- | tcl/target/stm32l4x.cfg | 2 |
2 files changed, 19 insertions, 8 deletions
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index db68539..fa0c48b 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -27,18 +27,22 @@ /* STM32L4xxx series for reference. * - * RM0351 - * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00083560.pdf + * RM0351 (STM32L4x5/STM32L4x6) + * http://www.st.com/resource/en/reference_manual/dm00083560.pdf * - * STM32L476RG Datasheet (for erase timing) - * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00108832.pdf + * RM0394 (STM32L43x/44x/45x/46x) + * http://www.st.com/resource/en/reference_manual/dm00151940.pdf * + * STM32L476RG Datasheet (for erase timing) + * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf * - * The device has normally two banks, but on 512 and 256 kiB devices an - * option byte is available to map all sectors to the first bank. + * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices + * an option byte is available to map all sectors to the first bank. * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices * handlers do! * + * RM0394 devices have a single bank only. + * */ /* Erase time can be as high as 25ms, 10x this and assume it's toast... */ @@ -618,6 +622,9 @@ static int stm32l4_probe(struct flash_bank *bank) case 0x415: max_flash_size_in_kb = 1024; break; + case 0x462: + max_flash_size_in_kb = 512; + break; case 0x435: max_flash_size_in_kb = 256; break; @@ -725,8 +732,12 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size) device_str = "STM32L475/476/486"; break; + case 0x462: + device_str = "STM32L45x/46x"; + break; + case 0x435: - device_str = "STM32L43x"; + device_str = "STM32L43x/44x"; break; default: diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg index 9cad7c4..ccee48e 100644 --- a/tcl/target/stm32l4x.cfg +++ b/tcl/target/stm32l4x.cfg @@ -75,7 +75,7 @@ $_TARGETNAME configure -event reset-init { # Use MSI 24 MHz clock, compliant even with VOS == 2. # 3 WS compliant with VOS == 2 and 24 MHz. mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency) - mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10 + mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9 # Boost JTAG frequency adapter_khz 4000 } |