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authorEdward Fewell <efewell@ti.com>2018-12-05 17:54:42 -0600
committerTomas Vanek <vanekt@fbl.cz>2019-01-08 09:51:13 +0000
commit5fd1cb0e5b4ec60d34109febac25443a9394b8f1 (patch)
treec28fb35e1182c3de1accfeb47b3e693dec504d0b
parent615a066629656aaa375c50885ef2f1530d1a5465 (diff)
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icepick.cfg: add cancel reset bit to TAP register writes
The Agama family of devices (CC26x2/CC13x2) required an additional bit to be set when adding the core's TAP into the scan chain. The cancel reset bit 0x10000 tells the ICEPick to take the bus out of reset so that the other bits will take effect. This bit is a NOP on other devices and ICEPicks, so the change shouldn't adversely affect other devices. Change-Id: I9245eef0936ea7eea28ae84ab5e8ce05fa63af40 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4789 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
-rw-r--r--tcl/target/icepick.cfg6
1 files changed, 3 insertions, 3 deletions
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 0f160bb..a945bea 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -90,18 +90,18 @@ proc icepick_c_tapenable {jrc port} {
# And never to enter RESET, which will disable the TAPs.
# first enable power and clock for TAP
- icepick_c_router $jrc 1 0x2 $port 0x100048
+ icepick_c_router $jrc 1 0x2 $port 0x110048
# TRM states that the register should be read back here, skipped for now
# enable debug "default" mode
- icepick_c_router $jrc 1 0x2 $port 0x102048
+ icepick_c_router $jrc 1 0x2 $port 0x112048
# TRM states that debug enable and debug mode should be read back and
# confirmed - skipped for now
# Finally select the tap
- icepick_c_router $jrc 1 0x2 $port 0x102148
+ icepick_c_router $jrc 1 0x2 $port 0x112148
# Enter the bypass state
irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE