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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-02 17:34:35 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-02 17:34:35 +0000 |
| commit | 3878b1279399cbd1c57730f7410db4b7c01b15c4 (patch) | |
| tree | 7203fb146cf28ecc43071ffd3346e9da14ab6ad0 | |
| parent | cde17a42e94e638e6bc32c1a6993207df82d953d (diff) | |
| download | riscv-openocd-3878b1279399cbd1c57730f7410db4b7c01b15c4.zip riscv-openocd-3878b1279399cbd1c57730f7410db4b7c01b15c4.tar.gz riscv-openocd-3878b1279399cbd1c57730f7410db4b7c01b15c4.tar.bz2 | |
David Claffey <dnclaffey@gmail.com> tested with the Atheros reference design "PB44"
git-svn-id: svn://svn.berlios.de/openocd/trunk@2662 b42882b7-edfa-0310-969c-e2dbd0fdcd60
| -rw-r--r-- | tcl/target/ar71xx.cfg | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg new file mode 100644 index 0000000..f2f5289 --- /dev/null +++ b/tcl/target/ar71xx.cfg @@ -0,0 +1,56 @@ +# Atheros AR71xx MIPS 24Kc SoC. +# tested on PB44 refererence board + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +reset_config trst_and_srst + +set CHIPNAME ar71xx + +jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 + +set TARGETNAME [format "%s.cpu" $CHIPNAME] +target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME + +$TARGETNAME configure -event reset-init { + #setup PLL to lowest common denominator 300/300/150 setting + mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0 + mww 0xb8050000 0x800f40a3 # send to PLL + + #next command will reset for PLL changes to take effect + mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC) + reset halt # let openocd know that it is in the reset state + + #initialize_pll + mww 0xb8050000 0x800f0080 # set sw_update bit + mww 0xb8050008 0 # clear reset_switch bit + mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass + mww 0xb8050008 1 # set clock_switch bit + sleep 1 # wait for lock + + # Setup DDR config and flash mapping + mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0) + mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8) + + mww 0xb8000010 8 # force precharge all banks + mww 0xb8000010 1 # force EMRS update cycle + mww 0xb800000c 0 # clr ext. mode register + mww 0xb8000010 2 # force auto refresh all banks + mww 0xb8000010 8 # force precharge all banks + mww 0xb8000008 0x31 # set DDR mode value CAS=3 + mww 0xb8000010 1 # force EMRS update cycle + mww 0xb8000014 0x461b # DDR refresh value + mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff) + mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7) + mww 0xb8000020 0 + mww 0xb8000024 0 + mww 0xb8000028 0 +} + +# setup working area somewhere in RAM +$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 + +# serial SPI capable flash +# flash bank <driver> <base> <size> <chip_width> <bus_width> + |