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| author | Tomas Vanek <vanekt@fbl.cz> | 2021-12-08 22:11:32 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-12-18 17:23:04 +0000 |
| commit | 33fa237b2ffdfc24b7e0c0861ac7708b21431c8c (patch) | |
| tree | ea6a4de7566a08337a214826e444b29b66d6e906 | |
| parent | 1e07079dee083255eb84fdebdfd4ed4c30e82812 (diff) | |
| download | riscv-openocd-33fa237b2ffdfc24b7e0c0861ac7708b21431c8c.zip riscv-openocd-33fa237b2ffdfc24b7e0c0861ac7708b21431c8c.tar.gz riscv-openocd-33fa237b2ffdfc24b7e0c0861ac7708b21431c8c.tar.bz2 | |
target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32()
Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().
Use the helper.
Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d762918328 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c7171b (target/cortex_m: cumulate DHCSR sticky bits)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/cortex_m.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 5605dd0..7125e9e 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -397,11 +397,9 @@ static int cortex_m_store_core_reg_u32(struct target *target, /* check if value is written into register */ then = timeval_ms(); while (1) { - retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, - &cortex_m->dcb_dhcsr); + retval = cortex_m_read_dhcsr_atomic_sticky(target); if (retval != ERROR_OK) return retval; - cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr); if (cortex_m->dcb_dhcsr & S_REGRDY) break; if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) { |