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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2021-04-21 10:18:04 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2021-04-30 08:21:33 +0100 |
| commit | 2c4f7efbf6ca467121e96dd044b9fdf373774550 (patch) | |
| tree | 792fc9a795067a86a6196f2f7d8ee031cf48110f | |
| parent | ef0aa38c108be536deff73c299ba542e215a892f (diff) | |
| download | riscv-openocd-2c4f7efbf6ca467121e96dd044b9fdf373774550.zip riscv-openocd-2c4f7efbf6ca467121e96dd044b9fdf373774550.tar.gz riscv-openocd-2c4f7efbf6ca467121e96dd044b9fdf373774550.tar.bz2 | |
doc/openocd.texi: fix warning
fix the warning below by adding a '.' after xref in line 4517:
../code/doc/openocd.texi:4517: warning: `.' or `,' must follow @xref, not )
Change-Id: I6e529c7e83c9f912e1dd899abf5f630c90b583d9
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6174
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 4dd3a33..21b6e95 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4500,7 +4500,7 @@ a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs. It's possible to connect a GDB client to this target (the GDB port has to be -specified, @xref{gdbportoverride,,option -gdb-port}), and a fake ARM core will +specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will be emulated to comply to GDB remote protocol. @item @code{mips_m4k} -- a MIPS core. @item @code{mips_mips64} -- a MIPS64 core. |