Merge up to fd7b66c5eb038185b72953821204ec9bb8ce49d1 from upstream

Backports the fix for #1131.

Commit 0bf3373 ("target/breakpoints: Use 'unsigned int' for length")
introduces a bug.
Link: https://review.openocd.org/c/openocd/+/7056/comment/3c4d9185_83614e2a/

Change-Id: I9f5f67050698a83c27f84965f6de031e2cad492d

45 files changed, 1200 insertions, 868 deletions

diff --git a/README b/README
index 7d3f10d..950c71f 100644
--- a/README
+++ b/README
@@ -1,5 +1,4 @@
-Welcome to OpenOCD!
-===================
+# Welcome to OpenOCD!
 
 OpenOCD provides on-chip programming and debugging support with a
 layered architecture of JTAG interface and TAP support including:
@@ -26,33 +25,33 @@ This README file contains an overview of the following topics:
 - packaging tips.
 
 
-============================
-Quickstart for the impatient
-============================
+# Quickstart for the impatient
 
 If you have a popular board then just start OpenOCD with its config,
 e.g.:
 
-  openocd -f board/stm32f4discovery.cfg
+    openocd -f board/stm32f4discovery.cfg
 
 If you are connecting a particular adapter with some specific target,
 you need to source both the jtag interface and the target configs,
 e.g.:
 
-  openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
-          -f target/ti_calypso.cfg
+```
+openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
+        -f target/ti_calypso.cfg
+```
 
-  openocd -f interface/stlink.cfg -c "transport select hla_swd" \
-          -f target/stm32l0.cfg
+```
+openocd -f interface/stlink.cfg -c "transport select hla_swd" \
+        -f target/stm32l0.cfg
+```
 
 After OpenOCD startup, connect GDB with
 
-  (gdb) target extended-remote localhost:3333
+    (gdb) target extended-remote localhost:3333
 
 
-=====================
-OpenOCD Documentation
-=====================
+# OpenOCD Documentation
 
 In addition to the in-tree documentation, the latest manuals may be
 viewed online at the following URLs:
@@ -71,35 +70,34 @@ by subscribing to the OpenOCD developer mailing list:
 
 	openocd-devel@lists.sourceforge.net
 
-Building the OpenOCD Documentation
-----------------------------------
+## Building the OpenOCD Documentation
 
 By default the OpenOCD build process prepares documentation in the
-"Info format" and installs it the standard way, so that "info openocd"
+"Info format" and installs it the standard way, so that `info openocd`
 can access it.
 
 Additionally, the OpenOCD User's Guide can be produced in the
 following different formats:
 
-  # If PDFVIEWER is set, this creates and views the PDF User Guide.
-  make pdf && ${PDFVIEWER} doc/openocd.pdf
+If `PDFVIEWER` is set, this creates and views the PDF User Guide.
 
-  # If HTMLVIEWER is set, this creates and views the HTML User Guide.
-  make html && ${HTMLVIEWER} doc/openocd.html/index.html
+    make pdf && ${PDFVIEWER} doc/openocd.pdf
+
+If `HTMLVIEWER` is set, this creates and views the HTML User Guide.
+
+    make html && ${HTMLVIEWER} doc/openocd.html/index.html
 
 The OpenOCD Developer Manual contains information about the internal
 architecture and other details about the code:
 
-  # NB! make sure doxygen is installed, type doxygen --version
-  make doxygen && ${HTMLVIEWER} doxygen/index.html
+Note: make sure doxygen is installed, type doxygen --version
 
+    make doxygen && ${HTMLVIEWER} doxygen/index.html
 
-==================
-Supported hardware
-==================
 
-JTAG adapters
--------------
+# Supported hardware
+
+## JTAG adapters
 
 AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
 Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
@@ -116,8 +114,7 @@ sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster,
 USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe,
 Xverve.
 
-Debug targets
--------------
+## Debug targets
 
 ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
 FA526, Feroceon/Dragonite, XScale.
@@ -125,8 +122,7 @@ ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
 ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,
 Xtensa.
 
-Flash drivers
--------------
+## Flash drivers
 
 ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI,
 DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI,
@@ -140,12 +136,9 @@ TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF,
 XMC1xxx, XMC4xxx.
 
 
-==================
-Installing OpenOCD
-==================
+# Installing OpenOCD
 
-A Note to OpenOCD Users
------------------------
+## A Note to OpenOCD Users
 
 If you would rather be working "with" OpenOCD rather than "on" it, your
 operating system or JTAG interface supplier may provide binaries for
@@ -164,8 +157,7 @@ Users of these binary versions of OpenOCD must contact their Packager to
 ask for support or newer versions of the binaries; the OpenOCD
 developers do not support packages directly.
 
-A Note to OpenOCD Packagers
----------------------------
+## A Note to OpenOCD Packagers
 
 You are a PACKAGER of OpenOCD if you:
 
@@ -192,11 +184,9 @@ suggestions:
 - Use "ftdi" interface adapter driver for the FTDI-based devices.
 
 
-================
-Building OpenOCD
-================
+# Building OpenOCD
 
-The INSTALL file contains generic instructions for running 'configure'
+The INSTALL file contains generic instructions for running `configure`
 and compiling the OpenOCD source code. That file is provided by
 default for all GNU autotools packages. If you are not familiar with
 the GNU autotools, then you should read those instructions first.
@@ -204,8 +194,7 @@ the GNU autotools, then you should read those instructions first.
 The remainder of this document tries to provide some instructions for
 those looking for a quick-install.
 
-OpenOCD Dependencies
---------------------
+## OpenOCD Dependencies
 
 GCC or Clang is currently required to build OpenOCD. The developers
 have begun to enforce strict code warnings (-Wall, -Werror, -Wextra,
@@ -250,8 +239,7 @@ Optional development script checkpatch needs:
 - python
 - python-ply
 
-Permissions delegation
-----------------------
+## Permissions delegation
 
 Running OpenOCD with root/administrative permissions is strongly
 discouraged for security reasons.
@@ -268,89 +256,81 @@ For parport adapters on Windows you need to run install_giveio.bat
 (it's also possible to use "ioperm" with Cygwin instead) to give
 ordinary users permissions for accessing the "LPT" registers directly.
 
-Compiling OpenOCD
------------------
+## Compiling OpenOCD
 
 To build OpenOCD, use the following sequence of commands:
 
-  ./bootstrap (when building from the git repository)
-  ./configure [options]
-  make
-  sudo make install
+    ./bootstrap
+    ./configure [options]
+    make
+    sudo make install
 
-The 'configure' step generates the Makefiles required to build
+The `bootstrap` command is only necessary when building from the Git repository. The `configure` step generates the Makefiles required to build
 OpenOCD, usually with one or more options provided to it. The first
 'make' step will build OpenOCD and place the final executable in
-'./src/'. The final (optional) step, ``make install'', places all of
+'./src/'. The final (optional) step, `make install`, places all of
 the files in the required location.
 
-To see the list of all the supported options, run
-  ./configure --help
+To see the list of all the supported options, run `./configure --help`
 
-Cross-compiling Options
------------------------
+## Cross-compiling Options
 
 Cross-compiling is supported the standard autotools way, you just need
 to specify the cross-compiling target triplet in the --host option,
 e.g. for cross-building for Windows 32-bit with MinGW on Debian:
 
-  ./configure --host=i686-w64-mingw32 [options]
+    ./configure --host=i686-w64-mingw32 [options]
 
 To make pkg-config work nicely for cross-compiling, you might need an
 additional wrapper script as described at
 
-  https://autotools.io/pkgconfig/cross-compiling.html
+    https://autotools.io/pkgconfig/cross-compiling.html
 
 This is needed to tell pkg-config where to look for the target
 libraries that OpenOCD depends on. Alternatively, you can specify
-*_CFLAGS and *_LIBS environment variables directly, see "./configure
---help" for the details.
+`*_CFLAGS` and `*_LIBS` environment variables directly, see `./configure
+--help` for the details.
 
 For a more or less complete script that does all this for you, see
 
-  contrib/cross-build.sh
+    contrib/cross-build.sh
 
-Parallel Port Dongles
----------------------
+## Parallel Port Dongles
 
 If you want to access the parallel port using the PPDEV interface you
-have to specify both --enable-parport AND --enable-parport-ppdev, since
+have to specify both `--enable-parport` and `--enable-parport-ppdev`, since
 the later option is an option to the parport driver.
 
-The same is true for the --enable-parport-giveio option, you have to
-use both the --enable-parport AND the --enable-parport-giveio option
+The same is true for the `--enable-parport-giveio` option, you have to
+use both the `--enable-parport` and the `--enable-parport-giveio` option
 if you want to use giveio instead of ioperm parallel port access
 method.
 
 
-==========================
-Obtaining OpenOCD From GIT
-==========================
+# Obtaining OpenOCD From GIT
 
 You can download the current GIT version with a GIT client of your
 choice from the main repository:
 
-   git://git.code.sf.net/p/openocd/code
+    git://git.code.sf.net/p/openocd/code
 
 You may prefer to use a mirror:
 
-   http://repo.or.cz/r/openocd.git
-   git://repo.or.cz/openocd.git
+    http://repo.or.cz/r/openocd.git
+    git://repo.or.cz/openocd.git
 
 Using the GIT command line client, you might use the following command
 to set up a local copy of the current repository (make sure there is no
 directory called "openocd" in the current directory):
 
-   git clone git://git.code.sf.net/p/openocd/code openocd
-
-Then you can update that at your convenience using
+    git clone git://git.code.sf.net/p/openocd/code openocd
 
-   git pull
+Then you can update that at your convenience using `git pull`.
 
 There is also a gitweb interface, which you can use either to browse
 the repository or to download arbitrary snapshots using HTTP:
 
-   http://repo.or.cz/w/openocd.git
+    http://repo.or.cz/w/openocd.git
 
 Snapshots are compressed tarballs of the source tree, about 1.3 MBytes
 each at this writing.
diff --git a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
index 2246a36..d20d9be 100644
--- a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
+++ b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
@@ -1,249 +1,248 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
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+0x0e,0x06,0x36,0x0e,0x03,0x1c,0x03,0x25,0x03,0xe0,0x62,0x1e,0x00,0x2c,0x3c,0xd0,
+0x14,0x1c,0x01,0x33,0x5a,0x1e,0x16,0x70,0x2b,0x42,0xf6,0xd1,0x03,0x2c,0x2b,0xd9,
+0xff,0x25,0x0d,0x40,0x2a,0x02,0x15,0x43,0x2a,0x04,0x15,0x43,0x0f,0x2c,0x15,0xd9,
+0x27,0x1c,0x10,0x3f,0x3f,0x09,0x1e,0x1c,0x3a,0x01,0x10,0x36,0xb6,0x18,0x1a,0x1c,
+0x15,0x60,0x55,0x60,0x95,0x60,0xd5,0x60,0x10,0x32,0xb2,0x42,0xf8,0xd1,0x01,0x37,
+0x3f,0x01,0x0f,0x22,0xdb,0x19,0x14,0x40,0x03,0x2c,0x0d,0xd9,0x27,0x1f,0xbf,0x08,
+0xba,0x00,0x1e,0x1d,0xb6,0x18,0x1a,0x1c,0x20,0xc2,0xb2,0x42,0xfc,0xd1,0x01,0x37,
+0xbf,0x00,0x03,0x22,0xdb,0x19,0x14,0x40,0x00,0x2c,0x06,0xd0,0x0a,0x06,0x12,0x0e,
+0x1c,0x19,0x1a,0x70,0x01,0x33,0xa3,0x42,0xfb,0xd1,0xf0,0xbc,0x02,0xbc,0x08,0x47,
+0x14,0x1c,0x03,0x1c,0xc2,0xe7,0xc0,0x46,0x08,0xb5,0x04,0x4b,0x00,0x2b,0x02,0xd0,
+0x03,0x48,0x00,0xf0,0x9b,0xf8,0x08,0xbc,0x01,0xbc,0x00,0x47,0x00,0x00,0x00,0x00,
+0xc1,0x0d,0x00,0x20,0xf0,0xb5,0x5f,0x46,0x56,0x46,0x4d,0x46,0x44,0x46,0xf0,0xb4,
+0x43,0x4b,0x1b,0x68,0x85,0xb0,0x01,0x93,0x49,0x33,0xff,0x33,0x02,0x90,0x03,0x93,
+0x0f,0x1c,0x01,0x98,0xa4,0x21,0x49,0x00,0x42,0x58,0x90,0x46,0x00,0x2a,0x4b,0xd0,
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+0x88,0x35,0xed,0x18,0xc6,0x20,0xc4,0x23,0x01,0x36,0x5b,0x00,0x40,0x00,0xb6,0x00,
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+0x1b,0x68,0xbb,0x42,0x05,0xd0,0x04,0x3d,0x04,0x3e,0x01,0x3c,0x29,0xd3,0x00,0x2f,
+0xf4,0xd1,0x41,0x46,0x4a,0x68,0x01,0x3a,0x33,0x68,0xa2,0x42,0x30,0xd0,0x00,0x22,
+0x32,0x60,0x00,0x2b,0xef,0xd0,0x40,0x46,0x59,0x46,0x40,0x68,0x01,0x22,0x09,0x68,
+0xa2,0x40,0x00,0x90,0x11,0x42,0x20,0xd0,0x50,0x46,0x00,0x68,0x10,0x42,0x21,0xd1,
+0x02,0x98,0x29,0x68,0x00,0xf0,0x40,0xf8,0x41,0x46,0x49,0x68,0x00,0x9a,0x91,0x42,
+0xb7,0xd1,0x4a,0x46,0x12,0x68,0x42,0x45,0xb3,0xd1,0x04,0x3d,0x04,0x3e,0x01,0x3c,
+0xd5,0xd2,0x18,0x4a,0x00,0x2a,0x11,0xd1,0x05,0xb0,0x3c,0xbc,0x90,0x46,0x99,0x46,
+0xa2,0x46,0xab,0x46,0xf0,0xbc,0x01,0xbc,0x00,0x47,0x00,0xf0,0x25,0xf8,0xe3,0xe7,
+0x4c,0x60,0xce,0xe7,0x28,0x68,0x00,0xf0,0x1f,0xf8,0xdd,0xe7,0x43,0x46,0x5b,0x68,
+0x40,0x46,0x00,0x2b,0x0d,0xd1,0x03,0x68,0x00,0x2b,0x0e,0xd0,0x49,0x46,0x0b,0x60,
+0xaf,0xf3,0x00,0x80,0x4b,0x46,0x1a,0x68,0x90,0x46,0x41,0x46,0x00,0x29,0x91,0xd1,
+0xda,0xe7,0x03,0x68,0xc1,0x46,0x98,0x46,0xf7,0xe7,0x00,0x23,0xfa,0xe7,0xc0,0x46,
+0xfc,0x0e,0x00,0x20,0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0x08,0xb5,0x01,0x1c,
+0x00,0x22,0x00,0x20,0x00,0x23,0x00,0xf0,0x1f,0xf8,0x08,0xbc,0x02,0xbc,0x08,0x47,
+0x38,0xb5,0x0a,0x4b,0x0a,0x4d,0xed,0x1a,0xad,0x10,0x0a,0xd0,0x01,0x3d,0xac,0x00,
+0xe4,0x18,0x00,0xe0,0x01,0x3d,0x23,0x68,0x00,0xf0,0x0c,0xf8,0x04,0x3c,0x00,0x2d,
+0xf8,0xd1,0x00,0xf0,0x71,0xf8,0x38,0xbc,0x01,0xbc,0x00,0x47,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0xf0,0xb5,0x4f,0x46,0x46,0x46,0xc0,0xb4,
+0x98,0x46,0x2c,0x4b,0xa4,0x25,0x1b,0x68,0x6d,0x00,0x5c,0x59,0x83,0xb0,0x06,0x1c,
+0x0f,0x1c,0x91,0x46,0x01,0x93,0x00,0x2c,0x46,0xd0,0x65,0x68,0x1f,0x2d,0x1a,0xdd,
+0x25,0x4b,0x00,0x2b,0x02,0xd1,0x01,0x20,0x40,0x42,0x1c,0xe0,0xc8,0x20,0x40,0x00,
+0xaf,0xf3,0x00,0x80,0x04,0x1e,0xf6,0xd0,0x00,0x25,0x45,0x60,0xa4,0x23,0x01,0x98,
+0x5b,0x00,0xc0,0x58,0x01,0x99,0x20,0x60,0xcc,0x50,0xc4,0x23,0x5b,0x00,0xe5,0x50,
+0xc6,0x23,0x5b,0x00,0xe5,0x50,0x00,0x2e,0x0c,0xd1,0x6b,0x1c,0x02,0x35,0xad,0x00,
+0x63,0x60,0x2f,0x51,0x00,0x20,0x03,0xb0,0x0c,0xbc,0x90,0x46,0x99,0x46,0xf0,0xbc,
+0x02,0xbc,0x08,0x47,0xab,0x00,0xe3,0x18,0x88,0x22,0x48,0x46,0x98,0x50,0xc4,0x20,
+0x40,0x00,0x22,0x18,0x10,0x68,0x01,0x21,0xa9,0x40,0x08,0x43,0x10,0x60,0x84,0x22,
+0x52,0x00,0x40,0x46,0x98,0x50,0x02,0x2e,0xdf,0xd1,0xc6,0x22,0x52,0x00,0xa3,0x18,
+0x18,0x68,0x01,0x43,0x19,0x60,0xd8,0xe7,0x1c,0x1c,0x4d,0x34,0xff,0x34,0x5c,0x51,
+0xb3,0xe7,0xc0,0x46,0xfc,0x0e,0x00,0x20,0x00,0x00,0x00,0x00,0xf8,0xb5,0xc0,0x46,
+0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,
+0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xc8,0xf1,0xff,0x7f,0x01,0x00,0x00,0x00,
+0x18,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,
+0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf4,0x11,0x00,0x20,
+0x5c,0x12,0x00,0x20,0xc4,0x12,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x0e,0x00,0x20,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -307,8 +306,9 @@
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
-0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x08,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
+0x69,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
index 9adb919..345079b 100644
--- a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
+++ b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
@@ -1,258 +1,257 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
 0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48,
-0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb,
-0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20,
-0xfc,0x13,0x00,0x20,0x08,0xb5,0x07,0x4b,0x07,0x48,0x03,0x33,0x1b,0x1a,0x06,0x2b,
-0x04,0xd9,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x5c,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x08,0x48,0x09,0x49,0x09,0x1a,0x89,0x10,0x08,0xb5,0xcb,0x0f,0x59,0x18,0x49,0x10,
-0x04,0xd0,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x44,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x10,0xb5,0x08,0x4c,0x23,0x78,0x00,0x2b,0x09,0xd1,0xff,0xf7,0xcb,0xff,0x06,0x4b,
+0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xff,0xf6,
+0xfa,0xaf,0x00,0xf0,0x71,0xf9,0xfe,0xe7,0xe8,0x0e,0x00,0x20,0x4c,0x13,0x00,0x20,
+0xf4,0x13,0x00,0x20,0x10,0xb5,0x07,0x4c,0x23,0x78,0x00,0x2b,0x07,0xd1,0x06,0x4b,
 0x00,0x2b,0x02,0xd0,0x05,0x48,0xaf,0xf3,0x00,0x80,0x01,0x23,0x23,0x70,0x10,0xbc,
-0x01,0xbc,0x00,0x47,0x54,0x13,0x00,0x20,0x00,0x00,0x00,0x00,0xe0,0x0e,0x00,0x20,
-0x08,0xb5,0x0b,0x4b,0x00,0x2b,0x03,0xd0,0x0a,0x48,0x0b,0x49,0xaf,0xf3,0x00,0x80,
-0x0a,0x48,0x03,0x68,0x00,0x2b,0x04,0xd1,0xff,0xf7,0xc2,0xff,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0x07,0x4b,0x00,0x2b,0xf7,0xd0,0x00,0xf0,0x0c,0xf8,0xf4,0xe7,0xc0,0x46,
-0x00,0x00,0x00,0x00,0xe0,0x0e,0x00,0x20,0x58,0x13,0x00,0x20,0x4c,0x13,0x00,0x20,
-0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0xd4,0x30,0x9f,0xe5,0x00,0x00,0x53,0xe3,
-0xc8,0x30,0x9f,0x05,0x03,0xd0,0xa0,0xe1,0x00,0x20,0x0f,0xe1,0x0f,0x00,0x12,0xe3,
-0x15,0x00,0x00,0x0a,0xd1,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0xaa,0x4d,0xe2,
-0x0a,0x30,0xa0,0xe1,0xd7,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0x3a,0x43,0xe2,
-0xdb,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0x3a,0x43,0xe2,0xd2,0xf0,0x21,0xe3,
-0x03,0xd0,0xa0,0xe1,0x02,0x3a,0x43,0xe2,0xd3,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,
-0x02,0x39,0x43,0xe2,0xff,0x30,0xc3,0xe3,0xff,0x3c,0xc3,0xe3,0x04,0x30,0x03,0xe5,
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-0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0e,0x33,0xcd,0xab,0x34,0x12,0x6d,0xe6,0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -307,8 +306,9 @@
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
-0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,
+0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x6d,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/cc26xx/flash.c b/contrib/loaders/flash/cc26xx/flash.c
index affd029..6410549 100644
--- a/contrib/loaders/flash/cc26xx/flash.c
+++ b/contrib/loaders/flash/cc26xx/flash.c
@@ -42,7 +42,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
 *
 ******************************************************************************/
 static void issue_fsm_command(flash_state_command_t command);
-static void enable_sectors_for_write(void);
+static void enable_sectors_for_write(uint32_t);
 static uint32_t scale_cycle_values(uint32_t specified_timing,
 	uint32_t scale_value);
 static void set_write_mode(void);
@@ -80,42 +80,51 @@ uint32_t flash_bank_erase(bool force_precondition)
 	uint32_t error_return;
 	uint32_t sector_address;
 	uint32_t reg_val;
+	uint32_t bank_no;
+	uint32_t top_bank_start_addr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) &
+					FLASH_FCFG_B1_START_B1_START_ADDR_M)
+					>> FLASH_FCFG_B1_START_B1_START_ADDR_S;
 
-	/* Enable all sectors for erase. */
-	enable_sectors_for_write();
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
+		/* Enable all sectors for erase. */
+		enable_sectors_for_write(bank_no);
 
-	/* Clear the Status register. */
-	issue_fsm_command(FAPI_CLEAR_STATUS);
+		/* Clear the Status register. */
+		issue_fsm_command(FAPI_CLEAR_STATUS);
 
-	/* Enable erase of all sectors and enable precondition if required. */
-	reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
-	if (force_precondition)
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
-			FLASH_FSM_ST_MACHINE_DO_PRECOND;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Enable erase of all sectors and enable precondition if required. */
+		reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
+		if (force_precondition)
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
+				FLASH_FSM_ST_MACHINE_DO_PRECOND;
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
 
-	/* Issue the bank erase command to the FSM. */
-	issue_fsm_command(FAPI_ERASE_BANK);
+		// Write address to FADDR register.
+		HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no * top_bank_start_addr);
 
-	/* Wait for erase to finish. */
-	while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
-		;
+		/* Issue the bank erase command to the FSM. */
+		issue_fsm_command(FAPI_ERASE_BANK);
 
-	/* Update status. */
-	error_return = flash_check_fsm_for_error();
+		/* Wait for erase to finish. */
+		while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
+			;
 
-	/* Disable sectors for erase. */
-	flash_disable_sectors_for_write();
+		/* Update status. */
+		error_return = flash_check_fsm_for_error();
 
-	/* Set configured precondition mode since it may have been forced on. */
-	if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
-		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
-			~FLASH_FSM_ST_MACHINE_DO_PRECOND;
-		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Set configured precondition mode since it may have been forced on. */
+		if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
+				~FLASH_FSM_ST_MACHINE_DO_PRECOND;
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		}
+
+		if (error_return != FAPI_STATUS_SUCCESS)
+			break;
 	}
 
 	/* Program security data to default values in the customer configuration */
@@ -128,6 +137,9 @@ uint32_t flash_bank_erase(bool force_precondition)
 							CCFG_SIZE_SECURITY);
 	}
 
+	/* Disable sectors for erase. */
+	flash_disable_sectors_for_write();
+
 	/* Return status of operation. */
 	return error_return;
 }
@@ -161,23 +173,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
 ******************************************************************************/
 void flash_disable_sectors_for_write(void)
 {
+	uint32_t bank_no;
+
 	/* Configure flash back to read mode */
 	set_read_mode();
 
-	/* Disable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
 
-	/* Disable all sectors for erase and programming. */
-	HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+		/* Select flash bank. */
+		HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
-	/* Enable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+		/* Disable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
 
-	/* Protect sectors from sector erase. */
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Disable all sectors for erase and programming. */
+		HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+
+		/* Enable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+
+		/* Protect sectors from sector erase. */
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+	}
+
+	// Select bank 0
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0;
 }
 
 /******************************************************************************
@@ -214,7 +237,7 @@ static void issue_fsm_command(flash_state_command_t command)
 * the FLASH_O_FSM_SECTOR1 register.
 *
 ******************************************************************************/
-static void enable_sectors_for_write(void)
+static void enable_sectors_for_write(uint32_t bank_no)
 {
 	/* Trim flash module for program/erase operation. */
 	trim_for_write();
@@ -223,7 +246,7 @@ static void enable_sectors_for_write(void)
 	set_write_mode();
 
 	/* Select flash bank. */
-	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00;
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
 	/* Disable Level 1 Protection. */
 	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h
index 07acf26..21df89b 100644
--- a/contrib/loaders/flash/cc26xx/flash.h
+++ b/contrib/loaders/flash/cc26xx/flash.h
@@ -247,6 +247,46 @@ static inline uint32_t flash_check_fsm_for_ready(void)
 }
 
 /******************************************************************************
+ *
+ * Get the number of banks
+ *
+ * This function returns the number of bank of the flash.
+ *
+ * Returns the number of banks
+ *
+ ******************************************************************************/
+static inline uint32_t flash_bank_count(void)
+{
+	uint32_t bank_count;
+
+	bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >>
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_S;
+
+	return bank_count;
+}
+
+/******************************************************************************
+ *
+ * Get the size of the bank.
+ *
+ * This function returns the size of the main bank in number of bytes.
+ *
+ * Returns the flash size in number of bytes.
+ *
+ ******************************************************************************/
+static inline uint8_t flash_bank_width(void)
+{
+	uint8_t bank_width;
+
+	bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >>
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3);
+
+	return bank_width;
+}
+
+/******************************************************************************
 *
 * Erase a flash sector.
 *
diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h b/contrib/loaders/flash/cc26xx/hw_regs.h
index 78c81be..753db17 100644
--- a/contrib/loaders/flash/cc26xx/hw_regs.h
+++ b/contrib/loaders/flash/cc26xx/hw_regs.h
@@ -116,6 +116,10 @@
 /* FMC Sequential Pump Information */
 #define FLASH_O_FSEQPMP                                             0x000020A8
 
+#define FLASH_O_FADDR                                               0x00002110
+
+#define FLASH_O_FWPWRITE0                                           0x00002120
+
 /* FMC FSM Command */
 #define FLASH_O_FSM_CMD                                             0x0000220C
 
@@ -179,9 +183,14 @@
 /* FMC FSM Sector Erased  2 */
 #define FLASH_O_FSM_SECTOR2                                         0x000022C4
 
+#define FLASH_O_FCFG_BANK                                           0x00002400
+
 /* FMC Flash Bank 0 Starting Address */
 #define FLASH_O_FCFG_B0_START                                       0x00002410
 
+/* FMC Flash Bank 1 Starting Address */
+#define FLASH_O_FCFG_B1_START                                       0x00002414
+
 /* FMC Flash Bank 0 Sector Size 0 */
 #define FLASH_O_FCFG_B0_SSIZE0                                      0x00002430
 
@@ -1353,4 +1362,16 @@
 * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
 #define AON_PMCTL_PWRCTL_EXT_REG_MODE                               0x00000002
 
+/* Field:   [3:0] MAIN_NUM_BANK */
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
+
+/* Field:  [23:0] B1_START_ADDR */
+#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
+
+/* Field:  [15:4] MAIN_BANK_WIDTH */
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
+
 #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */
diff --git a/doc/openocd.texi b/doc/openocd.texi
index ec862bd..3f22970 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8104,7 +8104,7 @@ The above example will read out the FLASH_OPTR register which contains the RDP
 option byte, Watchdog configuration, BOR level etc.
 @end deffn
 
-@deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
+@deffn {Command} {stm32l4x option_write} num reg_offset value [reg_mask]
 Write an option byte register of the stm32l4x device.
 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
@@ -9302,11 +9302,19 @@ power consumption (because the CPU is needlessly clocked).
 @deffn {Command} {resume} [address]
 Resume the target at its current code position,
 or the optional @var{address} if it is provided.
+
+@b{NOTE:} targets are expected to temporary disable breakpoints
+if they match the address of the current code position
+or the @var{address} provided by user.
 @end deffn
 
 @deffn {Command} {step} [address]
 Single-step the target at its current code position,
 or the optional @var{address} if it is provided.
+
+@b{NOTE:} targets are expected to temporary disable breakpoints
+if they match the address of the current code position
+or the @var{address} provided by user.
 @end deffn
 
 @anchor{resetcommand}
@@ -9562,11 +9570,12 @@ Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
 assigned to each channel to make them accessible to an unlimited number
 of TCP/IP connections.
 
-@deffn {Command} {rtt setup} address size ID
+@deffn {Command} {rtt setup} address size [ID]
 Configure RTT for the currently selected target.
 Once RTT is started, OpenOCD searches for a control block with the
 identifier @var{ID} starting at the memory address @var{address} within the next
 @var{size} bytes.
+ID defaults to the string "SEGGER RTT"
 @end deffn
 
 @deffn {Command} {rtt start}
@@ -9609,7 +9618,7 @@ on the target device.
 @example
 resume
 
-rtt setup 0x20000000 2048 "SEGGER RTT"
+rtt setup 0x20000000 2048
 rtt start
 
 rtt server start 9090 0
@@ -9650,6 +9659,12 @@ Add or replace help text on the given @var{command_name}.
 Add or replace usage text on the given @var{command_name}.
 @end deffn
 
+@deffn {Command} {ms}
+Returns current time since the Epoch in ms
+(See: @url{https://en.wikipedia.org/wiki/Epoch_(computing)}).
+Useful to compute delays in TCL.
+@end deffn
+
 @node Architecture and Core Commands
 @chapter Architecture and Core Commands
 @cindex Architecture Specific Commands
@@ -11822,8 +11837,8 @@ on @url{https://www.nxp.com}.
 @subsection Xtensa Configuration Commands
 
 @deffn {Config Command} {xtensa xtdef} (@option{LX}|@option{NX})
-Configure the Xtensa target architecture. Currently, Xtensa support is limited
-to LX6, LX7, and NX cores.
+Configure the Xtensa target architecture to LX or NX. Currently, Xtensa LX support
+is limited to LX6 and newer cores.
 @end deffn
 
 @deffn {Config Command} {xtensa xtopt} option value
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index fee3644..2d0a753 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -1038,6 +1038,7 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
 		bank->target = k_chip->target;
 		bank->driver = &kinetis_flash;
 		bank->default_padded_value = bank->erased_value = 0xff;
+		bank->minimal_write_gap = FLASH_WRITE_GAP_SECTOR;
 
 		snprintf(name, sizeof(name), "%s.%s%s",
 			 base_name, class, num);
diff --git a/src/flash/nor/sfdp.c b/src/flash/nor/sfdp.c
index 5bfb541..917f162 100644
--- a/src/flash/nor/sfdp.c
+++ b/src/flash/nor/sfdp.c
@@ -12,7 +12,6 @@
 #include "spi.h"
 #include "sfdp.h"
 
-#define SFDP_MAGIC			0x50444653
 #define SFDP_ACCESS_PROT	0xFF
 #define SFDP_BASIC_FLASH	0xFF00
 #define SFDP_4BYTE_ADDR		0xFF84
@@ -100,7 +99,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
 		goto err;
 
 	for (k = 0; k < nph; k++) {
-		uint8_t words = (pheaders[k].revision >> 24) & 0xFF;
+		unsigned int words = (pheaders[k].revision >> 24) & 0xFF;
 		uint16_t id = (((pheaders[k].ptr) >> 16) & 0xFF00) | (pheaders[k].revision & 0xFF);
 		uint32_t ptr = pheaders[k].ptr & 0xFFFFFF;
 
diff --git a/src/flash/nor/sfdp.h b/src/flash/nor/sfdp.h
index 1c9af32..0d43519 100644
--- a/src/flash/nor/sfdp.h
+++ b/src/flash/nor/sfdp.h
@@ -7,6 +7,8 @@
 #ifndef OPENOCD_FLASH_NOR_SFDP_H
 #define OPENOCD_FLASH_NOR_SFDP_H
 
+#define SFDP_MAGIC          0x50444653
+
 /* per JESD216D 'addr' is *byte* based but must be word aligned,
  * 'buffer' is word based, word aligned and always little-endian encoded,
  * in the flash, 'addr_len' is 3 or 4, 'dummy' ***usually*** 8
@@ -16,7 +18,7 @@
  *
  * buffer contents is supposed to be returned in ***host*** endianness */
 typedef int (*read_sfdp_block_t)(struct flash_bank *bank, uint32_t addr,
-	uint32_t words, uint32_t *buffer);
+	unsigned int words, uint32_t *buffer);
 
 extern int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
 	read_sfdp_block_t read_sfdp_block);
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index bb6e9ef..9235dd7 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -2622,7 +2622,7 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
 		.name = "option_write",
 		.handler = stm32l4_handle_option_write_command,
 		.mode = COMMAND_EXEC,
-		.usage = "bank_id reg_offset value mask",
+		.usage = "bank_id reg_offset value [mask]",
 		.help = "Write device option bit fields with provided value.",
 	},
 	{
diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c
index a1e1d34..df58f6c 100644
--- a/src/flash/nor/stmqspi.c
+++ b/src/flash/nor/stmqspi.c
@@ -1807,7 +1807,7 @@ err:
 
 /* Read SFDP parameter block */
 static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
-	uint32_t words, uint32_t *buffer)
+	unsigned int words, uint32_t *buffer)
 {
 	struct target *target = bank->target;
 	struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
@@ -1848,7 +1848,7 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
 		}
 	}
 
-	LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08" PRIx32 " dummy=%u",
+	LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08x dummy=%u",
 		__func__, addr, words, *dummy);
 
 	/* Abort any previous operation */
diff --git a/src/helper/binarybuffer.c b/src/helper/binarybuffer.c
index 3e09143..c25383d 100644
--- a/src/helper/binarybuffer.c
+++ b/src/helper/binarybuffer.c
@@ -74,7 +74,7 @@ bool buf_cmp(const void *_buf1, const void *_buf2, unsigned size)
 
 	unsigned last = size / 8;
 	if (memcmp(_buf1, _buf2, last) != 0)
-		return false;
+		return true;
 
 	unsigned trailing = size % 8;
 	if (!trailing)
@@ -175,19 +175,6 @@ uint32_t flip_u32(uint32_t value, unsigned int num)
 	return c;
 }
 
-static int ceil_f_to_u32(float x)
-{
-	if (x < 0)	/* return zero for negative numbers */
-		return 0;
-
-	uint32_t y = x;	/* cut off fraction */
-
-	if ((x - y) > 0.0)	/* if there was a fractional part, increase by one */
-		y++;
-
-	return y;
-}
-
 char *buf_to_hex_str(const void *_buf, unsigned buf_len)
 {
 	unsigned len_bytes = DIV_ROUND_UP(buf_len, 8);
@@ -205,154 +192,95 @@ char *buf_to_hex_str(const void *_buf, unsigned buf_len)
 	return str;
 }
 
-static bool str_has_hex_prefix(const char *s)
-{
-	/* Starts with "0x" or "0X" */
-	return (s[0] == '0') && (s[1] == 'x' || s[1] == 'X');
-}
-
-static bool str_has_octal_prefix(const char *s)
-{
-	/* - starts with '0',
-	 * - has at least two characters, and
-	 * - the second character is not 'x' or 'X' */
-	return (s[0] == '0') && (s[1] != '\0') && (s[1] != 'x') && (s[1] != 'X');
-}
-
-/**
- * Try to identify the radix of the number by looking at its prefix.
- * No further validation of the number is preformed.
+/*
+ * TCL standard prefix is '0b', '0o', '0d' or '0x' respectively for binary,
+ * octal, decimal or hexadecimal.
+ * The prefix '0' is interpreted by TCL <= 8.6 as octal, but is ignored and
+ * interpreted as part of a decimal number by JimTCL and by TCL >= 9.
  */
-static unsigned int str_radix_guess(const char *str)
+int str_to_buf(const char *str, void *_buf, unsigned int buf_bitsize)
 {
 	assert(str);
+	assert(_buf);
+	assert(buf_bitsize > 0);
 
-	if (str_has_hex_prefix(str))
-		return 16;
-
-	if (str_has_octal_prefix(str))
-		return 8;
-
-	/* Otherwise assume a decadic number. */
-	return 10;
-}
-
-/** Strip leading "0x" or "0X" from hex numbers or "0" from octal numbers. */
-static void str_strip_number_prefix_if_present(const char **_str, unsigned int radix)
-{
-	assert(radix == 16 || radix == 10 || radix == 8);
-	assert(_str);
-
-	const char *str = *_str;
-	assert(str);
-
-	if (radix == 16 && str_has_hex_prefix(str))
-		str += 2;
-	else if (radix == 8 && str_has_octal_prefix(str))
-		str += 1;
-
-	/* No prefix to strip for radix == 10. */
-
-	*_str = str;
-}
-
-int str_to_buf(const char *str, void *_buf, unsigned int buf_len,
-	unsigned int radix, unsigned int *_detected_radix)
-{
-	assert(radix == 0 || radix == 8 || radix == 10 || radix == 16);
-
-	if (radix == 0)
-		radix = str_radix_guess(str);
-
-	if (_detected_radix)
-		*_detected_radix = radix;
-
-	str_strip_number_prefix_if_present(&str, radix);
+	uint8_t *buf = _buf;
+	unsigned int radix = 10; /* default when no prefix */
+
+	if (str[0] == '0') {
+		switch (str[1]) {
+		case 'b':
+		case 'B':
+			radix = 2;
+			str += 2;
+			break;
+		case 'o':
+		case 'O':
+			radix = 8;
+			str += 2;
+			break;
+		case 'd':
+		case 'D':
+			radix = 10;
+			str += 2;
+			break;
+		case 'x':
+		case 'X':
+			radix = 16;
+			str += 2;
+			break;
+		default:
+			break;
+		}
+	}
 
 	const size_t str_len = strlen(str);
 	if (str_len == 0)
 		return ERROR_INVALID_NUMBER;
 
-	float factor = 0.0;
-	if (radix == 16)
-		factor = 0.5;	/* log(16) / log(256) = 0.5 */
-	else if (radix == 10)
-		factor = 0.41524;	/* log(10) / log(256) = 0.41524 */
-	else if (radix == 8)
-		factor = 0.375;	/* log(8) / log(256) = 0.375 */
-	else
-		assert(false);
-
-	const unsigned int b256_len = ceil_f_to_u32(str_len * factor);
-
-	/* Allocate a buffer for digits in base-256 notation */
-	uint8_t *b256_buf = calloc(b256_len, 1);
-	if (!b256_buf) {
-		LOG_ERROR("Unable to allocate memory");
-		return ERROR_FAIL;
-	}
+	const size_t buf_len = DIV_ROUND_UP(buf_bitsize, 8);
+	memset(buf, 0, buf_len);
 
 	/* Go through the zero-terminated buffer
 	 * of input digits (ASCII) */
-	for (unsigned int i = 0; str[i]; i++) {
-		uint32_t tmp = str[i];
-		if ((tmp >= '0') && (tmp <= '9')) {
-			tmp = (tmp - '0');
-		} else if ((tmp >= 'a') && (tmp <= 'f')) {
-			tmp = (tmp - 'a' + 10);
-		} else if ((tmp >= 'A') && (tmp <= 'F')) {
-			tmp = (tmp - 'A' + 10);
+	for (; *str; str++) {
+		unsigned int tmp;
+		const char c = *str;
+
+		if ((c >= '0') && (c <= '9')) {
+			tmp = c - '0';
+		} else if ((c >= 'a') && (c <= 'f')) {
+			tmp = c - 'a' + 10;
+		} else if ((c >= 'A') && (c <= 'F')) {
+			tmp = c - 'A' + 10;
 		} else {
 			/* Characters other than [0-9,a-f,A-F] are invalid */
-			free(b256_buf);
 			return ERROR_INVALID_NUMBER;
 		}
 
-		if (tmp >= radix) {
-			/* Encountered a digit that is invalid for the current radix */
-			free(b256_buf);
+		/* Error on invalid digit for current radix */
+		if (tmp >= radix)
 			return ERROR_INVALID_NUMBER;
-		}
 
-		/* Add the current digit (tmp) to the intermediate result
-		 * in b256_buf (base-256 digits) */
-		for (unsigned int j = 0; j < b256_len; j++) {
-			tmp += (uint32_t)b256_buf[j] * radix;
-			b256_buf[j] = (uint8_t)(tmp & 0xFFu);
+		/* Add the current digit (tmp) to the intermediate result in buf */
+		for (unsigned int j = 0; j < buf_len; j++) {
+			tmp += buf[j] * radix;
+			buf[j] = tmp & 0xFFu;
 			tmp >>= 8;
 		}
 
-		/* The b256_t buffer is large enough to contain the whole result. */
-		assert(tmp == 0);
-	}
-
-	/* The result must not contain more bits than buf_len. */
-	/* Check the whole bytes: */
-	for (unsigned int j = DIV_ROUND_UP(buf_len, 8); j < b256_len; j++) {
-		if (b256_buf[j] != 0x0) {
-			free(b256_buf);
+		/* buf should be large enough to contain the whole result. */
+		if (tmp != 0)
 			return ERROR_NUMBER_EXCEEDS_BUFFER;
-		}
-	}
-	/* Check the partial byte: */
-	if (buf_len % 8) {
-		const uint8_t mask = 0xFFu << (buf_len % 8);
-		if ((b256_buf[(buf_len / 8)] & mask) != 0x0) {
-			free(b256_buf);
-			return ERROR_NUMBER_EXCEEDS_BUFFER;
-		}
 	}
 
-	/* Copy the digits to the output buffer */
-	uint8_t *buf = _buf;
-	for (unsigned j = 0; j < DIV_ROUND_UP(buf_len, 8); j++) {
-		if (j < b256_len)
-			buf[j] = b256_buf[j];
-		else
-			buf[j] = 0;
+	/* Check the partial most significant byte */
+	if (buf_bitsize % 8) {
+		const uint8_t mask = 0xFFu << (buf_bitsize % 8);
+		if ((buf[buf_len - 1] & mask) != 0x0)
+			return ERROR_NUMBER_EXCEEDS_BUFFER;
 	}
 
-	free(b256_buf);
 	return ERROR_OK;
 }
 
diff --git a/src/helper/binarybuffer.h b/src/helper/binarybuffer.h
index 4413743..df41998 100644
--- a/src/helper/binarybuffer.h
+++ b/src/helper/binarybuffer.h
@@ -34,6 +34,7 @@
 static inline void buf_set_u32(uint8_t *_buffer,
 	unsigned first, unsigned num, uint32_t value)
 {
+	assert(num >= 1 && num <= 32);
 	uint8_t *buffer = _buffer;
 
 	if ((num == 32) && (first == 0)) {
@@ -64,6 +65,7 @@ static inline void buf_set_u32(uint8_t *_buffer,
 static inline void buf_set_u64(uint8_t *_buffer,
 	unsigned first, unsigned num, uint64_t value)
 {
+	assert(num >= 1 && num <= 64);
 	uint8_t *buffer = _buffer;
 
 	if ((num == 32) && (first == 0)) {
@@ -102,6 +104,7 @@ static inline void buf_set_u64(uint8_t *_buffer,
 static inline uint32_t buf_get_u32(const uint8_t *_buffer,
 	unsigned first, unsigned num)
 {
+	assert(num >= 1 && num <= 32);
 	const uint8_t *buffer = _buffer;
 
 	if ((num == 32) && (first == 0)) {
@@ -131,6 +134,7 @@ static inline uint32_t buf_get_u32(const uint8_t *_buffer,
 static inline uint64_t buf_get_u64(const uint8_t *_buffer,
 	unsigned first, unsigned num)
 {
+	assert(num >= 1 && num <= 64);
 	const uint8_t *buffer = _buffer;
 
 	if ((num == 32) && (first == 0)) {
@@ -194,15 +198,14 @@ void *buf_set_buf(const void *src, unsigned src_start,
 
 /**
  * Parse an unsigned number (provided as a zero-terminated string)
- * into a bit buffer whose size is buf_len bits.
+ * into a bit buffer whose size is buf_len bits. The base of the
+ * number is detected between decimal, hexadecimal and octal.
  * @param str Input number, zero-terminated string
  * @param _buf Output buffer, allocated by the caller
- * @param buf_len Output buffer size in bits
- * @param radix Base of the input number - 16, 10, 8 or 0.
- *              0 means auto-detect the radix.
+ * @param buf_bitsize Output buffer size in bits
+ * @returns Error on invalid or overflowing number
  */
-int str_to_buf(const char *str, void *_buf, unsigned int buf_len,
-	unsigned int radix, unsigned int *_detected_radix);
+int str_to_buf(const char *str, void *_buf, unsigned int buf_bitsize);
 
 char *buf_to_hex_str(const void *buf, unsigned size);
 
diff --git a/src/helper/command.c b/src/helper/command.c
index 15a9b4a..9078693 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -1360,37 +1360,18 @@ int command_parse_bool_arg(const char *in, bool *out)
 	return ERROR_COMMAND_SYNTAX_ERROR;
 }
 
-static const char *radix_to_str(unsigned int radix)
-{
-	switch (radix) {
-		case 16: return "hexadecimal";
-		case 10: return "decadic";
-		case 8: return "octal";
-	}
-	assert(false);
-	return "";
-}
-
-COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len,
-	unsigned int radix)
+COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len)
 {
 	assert(str);
 	assert(buf);
 
-	int ret = str_to_buf(str, buf, buf_len, radix, NULL);
+	int ret = str_to_buf(str, buf, buf_len);
 	if (ret == ERROR_OK)
 		return ret;
 
 	/* Provide a clear error message to the user */
 	if (ret == ERROR_INVALID_NUMBER) {
-		if (radix == 0) {
-			/* Any radix is accepted, so don't include it in the error message. */
-			command_print(CMD, "'%s' is not a valid number", str);
-		} else {
-			/* Specific radix is required - tell the user what it is. */
-			command_print(CMD, "'%s' is not a valid number (requiring %s number)",
-				str, radix_to_str(radix));
-		}
+		command_print(CMD, "'%s' is not a valid number", str);
 	} else if (ret == ERROR_NUMBER_EXCEEDS_BUFFER) {
 		command_print(CMD, "Number %s exceeds %u bits", str, buf_len);
 	} else {
diff --git a/src/helper/command.h b/src/helper/command.h
index 7a044e6..b224bd0 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -519,14 +519,12 @@ COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label);
 
 /**
  * Parse a number (base 10, base 16 or base 8) and store the result
- * into a bit buffer.
+ * into a bit buffer. Use the prefixes '0' and '0x' for base 8 and 16,
+ * otherwise defaults to base 10.
  *
  * In case of parsing error, a user-readable error message is produced.
- *
- * If radix = 0 is given, the function guesses the radix by looking at the number prefix.
  */
-COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len,
-	unsigned int radix);
+COMMAND_HELPER(command_parse_str_to_buf, const char *str, void *buf, unsigned int buf_len);
 
 /** parses an on/off command argument */
 #define COMMAND_PARSE_ON_OFF(in, out) \
diff --git a/src/jtag/drivers/cmsis_dap_usb_hid.c b/src/jtag/drivers/cmsis_dap_usb_hid.c
index 98ccc3e..aeec685 100644
--- a/src/jtag/drivers/cmsis_dap_usb_hid.c
+++ b/src/jtag/drivers/cmsis_dap_usb_hid.c
@@ -121,8 +121,12 @@ static int cmsis_dap_hid_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
 				break;
 
 			if (cur_dev->serial_number) {
-				size_t len = (strlen(serial) + 1) * sizeof(wchar_t);
-				wchar_t *wserial = malloc(len);
+				size_t len = mbstowcs(NULL, serial, 0) + 1;
+				wchar_t *wserial = malloc(len * sizeof(wchar_t));
+				if (!wserial) {
+					LOG_ERROR("unable to allocate serial number buffer");
+					return ERROR_FAIL;
+				}
 				mbstowcs(wserial, serial, len);
 
 				if (wcscmp(wserial, cur_dev->serial_number) == 0) {
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index a94f3a4..1b2fb4e 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -564,6 +564,20 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
 
 	if (!use_serial_number && !use_usb_address && !use_usb_location && num_devices > 1) {
 		LOG_ERROR("Multiple devices found, specify the desired device");
+		LOG_INFO("Found devices:");
+		for (size_t i = 0; devs[i]; i++) {
+			uint32_t serial;
+			ret = jaylink_device_get_serial_number(devs[i], &serial);
+			if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
+				continue;
+			} else if (ret != JAYLINK_OK) {
+				LOG_WARNING("jaylink_device_get_serial_number() failed: %s",
+					jaylink_strerror(ret));
+				continue;
+			}
+			LOG_INFO("Device %zu serial: %" PRIu32, i, serial);
+		}
+
 		jaylink_free_devices(devs, true);
 		jaylink_exit(jayctx);
 		return ERROR_JTAG_INIT_FAILED;
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 10a7dd3..624b4e4 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -89,7 +89,7 @@ static COMMAND_HELPER(handle_jtag_command_drscan_fields, struct scan_field *fiel
 		}
 
 		fields[field_count].out_value = t;
-		int ret = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[i + 1], t, bits, 0);
+		int ret = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[i + 1], t, bits);
 		if (ret != ERROR_OK)
 			return ret;
 		fields[field_count].in_value = t;
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index b2339bb..e82ab6f 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -140,7 +140,7 @@ static int hwthread_update_threads(struct rtos *rtos)
 					curr->state == TARGET_UNAVAILABLE)
 				continue;
 
-			threadid_t tid = threads_found + 1;
+			threadid_t tid = threadid_from_target(curr);
 			hwthread_fill_thread(rtos, curr, threads_found, tid);
 
 			/* find an interesting thread to set as current */
diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index 0ca664f..360ae9b 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -327,9 +327,7 @@ target_addr_t rtos_cortex_m_stack_align(struct target *target,
 
 	new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 		stacking->stack_registers_size;
-	xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ?
-			le_to_h_u32(&stack_data[xpsr_offset]) :
-			be_to_h_u32(&stack_data[xpsr_offset]);
+	xpsr = target_buffer_get_u32(target, &stack_data[xpsr_offset]);
 	if ((xpsr & ALIGN_NEEDED) != 0) {
 		LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
 			xpsr);
diff --git a/src/rtt/tcl.c b/src/rtt/tcl.c
index 2b8822f..bae71b6 100644
--- a/src/rtt/tcl.c
+++ b/src/rtt/tcl.c
@@ -19,8 +19,14 @@ COMMAND_HANDLER(handle_rtt_setup_command)
 {
 	struct rtt_source source;
 
-	if (CMD_ARGC != 3)
+	const char *DEFAULT_ID = "SEGGER RTT";
+	const char *selected_id;
+	if (CMD_ARGC < 2 || CMD_ARGC > 3)
 		return ERROR_COMMAND_SYNTAX_ERROR;
+	if (CMD_ARGC == 2)
+		selected_id = DEFAULT_ID;
+	else
+		selected_id = CMD_ARGV[2];
 
 	source.find_cb = &target_rtt_find_control_block;
 	source.read_cb = &target_rtt_read_control_block;
@@ -38,7 +44,7 @@ COMMAND_HANDLER(handle_rtt_setup_command)
 
 	rtt_register_source(source, get_current_target(CMD_CTX));
 
-	if (rtt_setup(address, size, CMD_ARGV[2]) != ERROR_OK)
+	if (rtt_setup(address, size, selected_id) != ERROR_OK)
 		return ERROR_FAIL;
 
 	return ERROR_OK;
@@ -218,7 +224,7 @@ static const struct command_registration rtt_subcommand_handlers[] = {
 		.handler = handle_rtt_setup_command,
 		.mode = COMMAND_ANY,
 		.help = "setup RTT",
-		.usage = "<address> <size> <ID>"
+		.usage = "<address> <size> [ID]"
 	},
 	{
 		.name = "start",
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 9129ace..3a5afc6 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -795,11 +795,12 @@ int dap_dp_init(struct adiv5_dap *dap)
 	dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 
 	/*
-	 * This write operation clears the sticky error bit in jtag mode only and
-	 * is ignored in swd mode. It also powers-up system and debug domains in
-	 * both jtag and swd modes, if not done before.
+	 * This write operation clears the sticky error and overrun bits in jtag
+	 * mode only and is ignored in swd mode. It also powers-up system and
+	 * debug domains in both jtag and swd modes, if not done before.
 	 */
-	retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
+	retval = dap_queue_dp_write(dap, DP_CTRL_STAT,
+				    dap->dp_ctrl_stat | SSTICKYERR | SSTICKYORUN);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1453,11 +1454,13 @@ static const struct dap_part_nums {
 	{ ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
 	{ ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
 	{ ARM_ID, 0x4b8, "Cortex-R52 ROM",             "(ROM Table)", },
+	{ ARM_ID, 0x4bd, "Cortex-R52+ ROM",            "(ROM Table)", },
 	{ ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
 	{ ARM_ID, 0x4c3, "Cortex-M3 ROM",              "(ROM Table)", },
 	{ ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
 	{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM",          "(Private Peripheral Bus ROM Table)", },
 	{ ARM_ID, 0x4c8, "Cortex-M7 ROM",              "(ROM Table)", },
+	{ ARM_ID, 0x4c9, "STAR ROM",                   "(ROM Table)", },
 	{ ARM_ID, 0x4e0, "Cortex-A35 ROM",             "(v7 Memory Map ROM Table)", },
 	{ ARM_ID, 0x4e4, "Cortex-A76 ROM",             "(ROM Table)", },
 	{ ARM_ID, 0x906, "CoreSight CTI",              "(Cross Trigger)", },
@@ -1499,6 +1502,7 @@ static const struct dap_part_nums {
 	{ ARM_ID, 0x9ae, "Cortex-A17 PMU",             "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9af, "Cortex-A15 PMU",             "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
+	{ ARM_ID, 0x9bb, "Cortex-R52+ PMU/CTI/ETM",    "(Performance Monitor Unit/Cross Trigger/ETM)", },
 	{ ARM_ID, 0x9b7, "Cortex-R7 PMU",              "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9d3, "Cortex-A53 PMU",             "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
@@ -1533,6 +1537,10 @@ static const struct dap_part_nums {
 	{ ARM_ID, 0xd0b, "Cortex-A76 Debug",           "(Debug Unit)", },
 	{ ARM_ID, 0xd0c, "Neoverse N1",                "(Debug Unit)", },
 	{ ARM_ID, 0xd13, "Cortex-R52 Debug",           "(Debug Unit)", },
+	{ ARM_ID, 0xd16, "Cortex-R52+ Debug",          "(Debug Unit)", },
+	{ ARM_ID, 0xd21, "STAR Debug",                 "(Debug Unit)", },
+	{ ARM_ID, 0xd22, "Cortex-M55 Debug",           "(Debug Unit)", },
+	{ ARM_ID, 0xd43, "Cortex-A65AE Debug",         "(Debug Unit)", },
 	{ ARM_ID, 0xd49, "Neoverse N2",                "(Debug Unit)", },
 	{ 0x017,  0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
 	{ 0x017,  0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
@@ -1552,6 +1560,9 @@ static const struct dap_part_nums {
 	{ 0x1eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
 	{ 0x1eb,  0x302, "Denver Debug",               "(Debug Unit)", },
 	{ 0x1eb,  0x402, "Denver PMU",                 "(Performance Monitor Unit)", },
+	{ 0x575,  0x132, "STAR SCS",                   "(System Control Space)", },
+	{ 0x575,  0x4d2, "Cortex-M52 ROM",             "(ROM Table)", },
+	{ 0x575,  0xd24, "Cortex-M52 Debug",           "(Debug Unit)", },
 };
 
 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c
index 7637ad0..97d1fb3 100644
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@@ -157,48 +157,44 @@ int arm_cti_clear_channel(struct arm_cti *self, uint32_t channel)
 	return arm_cti_write_reg(self, CTI_APPCLEAR, CTI_CHNL(channel));
 }
 
-static uint32_t cti_regs[28];
-
 static const struct {
 	uint32_t offset;
 	const char *label;
-	uint32_t *p_val;
 } cti_names[] = {
-	{ CTI_CTR,		"CTR",		&cti_regs[0] },
-	{ CTI_GATE,		"GATE",		&cti_regs[1] },
-	{ CTI_INEN0,	"INEN0",	&cti_regs[2] },
-	{ CTI_INEN1,	"INEN1",	&cti_regs[3] },
-	{ CTI_INEN2,	"INEN2",	&cti_regs[4] },
-	{ CTI_INEN3,	"INEN3",	&cti_regs[5] },
-	{ CTI_INEN4,	"INEN4",	&cti_regs[6] },
-	{ CTI_INEN5,	"INEN5",	&cti_regs[7] },
-	{ CTI_INEN6,	"INEN6",	&cti_regs[8] },
-	{ CTI_INEN7,	"INEN7",	&cti_regs[9] },
-	{ CTI_INEN8,	"INEN8",	&cti_regs[10] },
-	{ CTI_OUTEN0,	"OUTEN0",	&cti_regs[11] },
-	{ CTI_OUTEN1,	"OUTEN1",	&cti_regs[12] },
-	{ CTI_OUTEN2,	"OUTEN2",	&cti_regs[13] },
-	{ CTI_OUTEN3,	"OUTEN3",	&cti_regs[14] },
-	{ CTI_OUTEN4,	"OUTEN4",	&cti_regs[15] },
-	{ CTI_OUTEN5,	"OUTEN5",	&cti_regs[16] },
-	{ CTI_OUTEN6,	"OUTEN6",	&cti_regs[17] },
-	{ CTI_OUTEN7,	"OUTEN7",	&cti_regs[18] },
-	{ CTI_OUTEN8,	"OUTEN8",	&cti_regs[19] },
-	{ CTI_TRIN_STATUS,	"TRIN",	&cti_regs[20] },
-	{ CTI_TROUT_STATUS,	"TROUT", &cti_regs[21] },
-	{ CTI_CHIN_STATUS,	"CHIN",	&cti_regs[22] },
-	{ CTI_CHOU_STATUS,	"CHOUT", &cti_regs[23] },
-	{ CTI_APPSET,	"APPSET",	&cti_regs[24] },
-	{ CTI_APPCLEAR,	"APPCLR",	&cti_regs[25] },
-	{ CTI_APPPULSE,	"APPPULSE",	&cti_regs[26] },
-	{ CTI_INACK,	"INACK",	&cti_regs[27] },
+	{ CTI_CTR,	"CTR" },
+	{ CTI_GATE,	"GATE" },
+	{ CTI_INEN0,	"INEN0" },
+	{ CTI_INEN1,	"INEN1" },
+	{ CTI_INEN2,	"INEN2" },
+	{ CTI_INEN3,	"INEN3" },
+	{ CTI_INEN4,	"INEN4" },
+	{ CTI_INEN5,	"INEN5" },
+	{ CTI_INEN6,	"INEN6" },
+	{ CTI_INEN7,	"INEN7" },
+	{ CTI_INEN8,	"INEN8" },
+	{ CTI_OUTEN0,	"OUTEN0" },
+	{ CTI_OUTEN1,	"OUTEN1" },
+	{ CTI_OUTEN2,	"OUTEN2" },
+	{ CTI_OUTEN3,	"OUTEN3" },
+	{ CTI_OUTEN4,	"OUTEN4" },
+	{ CTI_OUTEN5,	"OUTEN5" },
+	{ CTI_OUTEN6,	"OUTEN6" },
+	{ CTI_OUTEN7,	"OUTEN7" },
+	{ CTI_OUTEN8,	"OUTEN8" },
+	{ CTI_TRIN_STATUS,	"TRIN" },
+	{ CTI_TROUT_STATUS,	"TROUT" },
+	{ CTI_CHIN_STATUS,	"CHIN" },
+	{ CTI_CHOU_STATUS,	"CHOUT" },
+	{ CTI_APPSET,	"APPSET" },
+	{ CTI_APPCLEAR,	"APPCLR" },
+	{ CTI_APPPULSE,	"APPPULSE" },
+	{ CTI_INACK,	"INACK" },
+	{ CTI_DEVCTL,	"DEVCTL" },
 };
 
 static int cti_find_reg_offset(const char *name)
 {
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(cti_names); i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(cti_names); i++) {
 		if (!strcmp(name, cti_names[i].label))
 			return cti_names[i].offset;
 	}
@@ -226,10 +222,11 @@ COMMAND_HANDLER(handle_cti_dump)
 	struct arm_cti *cti = CMD_DATA;
 	struct adiv5_ap *ap = cti->ap;
 	int retval = ERROR_OK;
+	uint32_t values[ARRAY_SIZE(cti_names)];
 
-	for (int i = 0; (retval == ERROR_OK) && (i < (int)ARRAY_SIZE(cti_names)); i++)
+	for (size_t i = 0; (retval == ERROR_OK) && (i < ARRAY_SIZE(cti_names)); i++)
 		retval = mem_ap_read_u32(ap,
-				cti->spot.base + cti_names[i].offset, cti_names[i].p_val);
+				cti->spot.base + cti_names[i].offset, &values[i]);
 
 	if (retval == ERROR_OK)
 		retval = dap_run(ap->dap);
@@ -237,9 +234,9 @@ COMMAND_HANDLER(handle_cti_dump)
 	if (retval != ERROR_OK)
 		return JIM_ERR;
 
-	for (int i = 0; i < (int)ARRAY_SIZE(cti_names); i++)
+	for (size_t i = 0; i < ARRAY_SIZE(cti_names); i++)
 		command_print(CMD, "%8.8s (0x%04"PRIx32") 0x%08"PRIx32,
-				cti_names[i].label, cti_names[i].offset, *cti_names[i].p_val);
+				cti_names[i].label, cti_names[i].offset, values[i]);
 
 	return JIM_OK;
 }
@@ -323,7 +320,6 @@ COMMAND_HANDLER(handle_cti_ack)
 
 	int retval = arm_cti_ack_events(cti, 1 << event);
 
-
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -437,6 +433,7 @@ static int cti_configure(struct jim_getopt_info *goi, struct arm_cti *cti)
 
 	return JIM_OK;
 }
+
 static int cti_create(struct jim_getopt_info *goi)
 {
 	struct command_context *cmd_ctx;
@@ -538,7 +535,6 @@ COMMAND_HANDLER(cti_handle_names)
 	return ERROR_OK;
 }
 
-
 static const struct command_registration cti_subcommand_handlers[] = {
 	{
 		.name = "create",
diff --git a/src/target/arm_cti.h b/src/target/arm_cti.h
index cfcde65..1513f02 100644
--- a/src/target/arm_cti.h
+++ b/src/target/arm_cti.h
@@ -39,6 +39,7 @@
 #define CTI_CHIN_STATUS		0x138
 #define CTI_CHOU_STATUS		0x13C
 #define CTI_GATE			0x140
+#define CTI_DEVCTL			0x150
 #define CTI_UNLOCK			0xFB0
 
 #define CTI_CHNL(x)			(1 << x)
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 77f7673..a1ef3bf 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -39,7 +39,7 @@ static int bpwp_unique_id;
 
 static int breakpoint_add_internal(struct target *target,
 	target_addr_t address,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	struct breakpoint *breakpoint = target->breakpoints;
@@ -102,7 +102,7 @@ fail:
 
 static int context_breakpoint_add_internal(struct target *target,
 	uint32_t asid,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	struct breakpoint *breakpoint = target->breakpoints;
@@ -152,7 +152,7 @@ static int context_breakpoint_add_internal(struct target *target,
 static int hybrid_breakpoint_add_internal(struct target *target,
 	target_addr_t address,
 	uint32_t asid,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	struct breakpoint *breakpoint = target->breakpoints;
@@ -208,7 +208,7 @@ static int hybrid_breakpoint_add_internal(struct target *target,
 
 int breakpoint_add(struct target *target,
 	target_addr_t address,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	if (target->smp && type == BKPT_HARD) {
@@ -232,7 +232,7 @@ int breakpoint_add(struct target *target,
 
 int context_breakpoint_add(struct target *target,
 	uint32_t asid,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	if (target->smp) {
@@ -256,7 +256,7 @@ int context_breakpoint_add(struct target *target,
 int hybrid_breakpoint_add(struct target *target,
 	target_addr_t address,
 	uint32_t asid,
-	uint32_t length,
+	unsigned int length,
 	enum breakpoint_type type)
 {
 	if (target->smp) {
@@ -542,7 +542,7 @@ struct breakpoint *breakpoint_find(struct target *target, target_addr_t address)
 }
 
 static int watchpoint_add_internal(struct target *target, target_addr_t address,
-		uint32_t length, enum watchpoint_rw rw, uint64_t value, uint64_t mask)
+		unsigned int length, enum watchpoint_rw rw, uint32_t value, uint32_t mask)
 {
 	struct watchpoint *watchpoint = target->watchpoints;
 	struct watchpoint **watchpoint_p = &target->watchpoints;
@@ -598,7 +598,7 @@ bye:
 	}
 
 	LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT
-			" of length 0x%8.8" PRIx32 " (WPID: %d)",
+			" of length 0x%8.8x (WPID: %d)",
 		watchpoint_rw_strings[(*watchpoint_p)->rw],
 		(*watchpoint_p)->address,
 		(*watchpoint_p)->length,
@@ -608,7 +608,7 @@ bye:
 }
 
 int watchpoint_add(struct target *target, target_addr_t address,
-		uint32_t length, enum watchpoint_rw rw, uint64_t value, uint64_t mask)
+		unsigned int length, enum watchpoint_rw rw, uint64_t value, uint64_t mask)
 {
 	if (target->smp) {
 		struct target_list *head;
diff --git a/src/target/breakpoints.h b/src/target/breakpoints.h
index 0ec65de..ac5d701 100644
--- a/src/target/breakpoints.h
+++ b/src/target/breakpoints.h
@@ -26,7 +26,7 @@ enum watchpoint_rw {
 struct breakpoint {
 	target_addr_t address;
 	uint32_t asid;
-	int length;
+	unsigned int length;
 	enum breakpoint_type type;
 	bool is_set;
 	unsigned int number;
@@ -40,7 +40,7 @@ struct breakpoint {
 
 struct watchpoint {
 	target_addr_t address;
-	uint32_t length;
+	unsigned int length;
 	uint64_t mask;
 	uint64_t value;
 	enum watchpoint_rw rw;
@@ -52,11 +52,12 @@ struct watchpoint {
 
 int breakpoint_clear_target(struct target *target);
 int breakpoint_add(struct target *target,
-		target_addr_t address, uint32_t length, enum breakpoint_type type);
+		target_addr_t address, unsigned int length, enum breakpoint_type type);
 int context_breakpoint_add(struct target *target,
-		uint32_t asid, uint32_t length, enum breakpoint_type type);
+		uint32_t asid, unsigned int length, enum breakpoint_type type);
 int hybrid_breakpoint_add(struct target *target,
-		target_addr_t address, uint32_t asid, uint32_t length, enum breakpoint_type type);
+		target_addr_t address, uint32_t asid, unsigned int length,
+		enum breakpoint_type type);
 int breakpoint_remove(struct target *target, target_addr_t address);
 int breakpoint_remove_all(struct target *target);
 
@@ -70,7 +71,7 @@ static inline void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int
 
 int watchpoint_clear_target(struct target *target);
 int watchpoint_add(struct target *target,
-		target_addr_t address, uint32_t length,
+		target_addr_t address, unsigned int length,
 		enum watchpoint_rw rw, uint64_t value, uint64_t mask);
 int watchpoint_remove(struct target *target, target_addr_t address);
 int watchpoint_remove_all(struct target *target);
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 726fca2..144f245 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -150,6 +150,7 @@ struct cortex_m_part_info {
 #define VC_CORERESET	BIT(0)
 
 /* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDSKEY	BIT(17)
 #define DSCSR_CDS		BIT(16)
 
 /* NVIC registers */
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index 22e1630..2afb4b0 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -421,4 +421,5 @@ struct target_type esp32s3_target = {
 	.deinit_target = esp_xtensa_target_deinit,
 
 	.commands = esp32s3_command_handlers,
+	.profiling = esp_xtensa_profiling,
 };
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index 11895d2..9b57f34 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -179,3 +179,75 @@ int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *break
 	return xtensa_breakpoint_remove(target, breakpoint);
 	/* flash breakpoints will be handled in another patch */
 }
+
+int esp_xtensa_profiling(struct target *target, uint32_t *samples,
+	uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
+{
+	struct timeval timeout, now;
+	struct xtensa *xtensa = target_to_xtensa(target);
+	int retval = ERROR_OK;
+	int res;
+
+	/* Vary samples per pass to avoid sampling a periodic function periodically */
+	#define MIN_PASS 200
+	#define MAX_PASS 1000
+
+	gettimeofday(&timeout, NULL);
+	timeval_add_time(&timeout, seconds, 0);
+
+	uint8_t buf[sizeof(uint32_t) * MAX_PASS];
+
+	/* Capture one sample to verify the register is present and working */
+	xtensa_queue_dbg_reg_read(xtensa, XDMREG_DEBUGPC, buf);
+	res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
+	if (res != ERROR_OK) {
+		LOG_TARGET_INFO(target, "Failed to read DEBUGPC, fallback to stop-and-go");
+		return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
+	} else if (buf[0] == 0 && buf[1] == 0 && buf[2] == 0 && buf[3] == 0) {
+		LOG_TARGET_INFO(target, "NULL DEBUGPC, fallback to stop-and-go");
+		return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
+	}
+
+	LOG_TARGET_INFO(target, "Starting XTENSA DEBUGPC profiling. Sampling as fast as we can...");
+
+	/* Make sure the target is running */
+	target_poll(target);
+	if (target->state == TARGET_HALTED)
+		retval = target_resume(target, 1, 0, 0, 0);
+
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "Error while resuming target");
+		return retval;
+	}
+
+	uint32_t sample_count = 0;
+
+	for (;;) {
+		uint32_t remaining = max_num_samples - sample_count;
+		uint32_t this_pass = rand() % (MAX_PASS - MIN_PASS) + MIN_PASS;
+		this_pass = this_pass > remaining ? remaining : this_pass;
+		for (uint32_t i = 0; i < this_pass; ++i)
+			xtensa_queue_dbg_reg_read(xtensa, XDMREG_DEBUGPC, buf + i * sizeof(uint32_t));
+		res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
+		if (res != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "Failed to read DEBUGPC!");
+			return res;
+		}
+
+		for (uint32_t i = 0; i < this_pass; ++i) {
+			uint32_t sample32 = buf_get_u32(buf + i * sizeof(uint32_t), 0, 32);
+			samples[sample_count++] = sample32;
+		}
+		gettimeofday(&now, NULL);
+		if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
+			LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count);
+			break;
+		}
+	}
+
+	*num_samples = sample_count;
+	return retval;
+
+	#undef MIN_PASS
+	#undef MAX_PASS
+}
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
index 00f67a3..56c903f 100644
--- a/src/target/espressif/esp_xtensa.h
+++ b/src/target/espressif/esp_xtensa.h
@@ -37,6 +37,9 @@ void esp_xtensa_queue_tdi_idle(struct target *target);
 int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
 int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
 int esp_xtensa_poll(struct target *target);
+int esp_xtensa_profiling(struct target *target, uint32_t *samples,
+	uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
+
 int esp_xtensa_on_halt(struct target *target);
 
 #endif	/* OPENOCD_TARGET_ESP_XTENSA_H */
diff --git a/src/target/target.c b/src/target/target.c
index b51f066..3f412a0 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3130,7 +3130,7 @@ COMMAND_HANDLER(handle_reg_command)
 			return ERROR_FAIL;
 		}
 
-		int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[1], buf, reg->size, 0);
+		int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf, CMD_ARGV[1], buf, reg->size);
 		if (retval != ERROR_OK) {
 			free(buf);
 			return retval;
@@ -3934,7 +3934,7 @@ static int handle_bp_command_list(struct command_invocation *cmd)
 }
 
 static int handle_bp_command_set(struct command_invocation *cmd,
-		target_addr_t addr, uint32_t asid, uint32_t length, int hw)
+		target_addr_t addr, uint32_t asid, unsigned int length, int hw)
 {
 	struct target *target = get_current_target(cmd->ctx);
 	int retval;
@@ -4051,7 +4051,7 @@ COMMAND_HANDLER(handle_wp_command)
 		while (watchpoint) {
 			char wp_type = (watchpoint->rw == WPT_READ ? 'r' : (watchpoint->rw == WPT_WRITE ? 'w' : 'a'));
 			command_print(CMD, "address: " TARGET_ADDR_FMT
-					", len: 0x%8.8" PRIx32
+					", len: 0x%8.8x"
 					", r/w/a: %c, value: 0x%8.8" PRIx64
 					", mask: 0x%8.8" PRIx64,
 					watchpoint->address,
@@ -4193,7 +4193,7 @@ static void write_gmon(uint32_t *samples, uint32_t sample_num, const char *filen
 			uint32_t start_address, uint32_t end_address, struct target *target, uint32_t duration_ms)
 {
 	uint32_t i;
-	FILE *f = fopen(filename, "w");
+	FILE *f = fopen(filename, "wb");
 	if (!f)
 		return;
 	write_string(f, "gmon");
@@ -4819,8 +4819,7 @@ COMMAND_HANDLER(handle_set_reg_command)
 			return ERROR_FAIL;
 		}
 
-		int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf,
-			reg_value, buf, reg->size, 0);
+		int retval = CALL_COMMAND_HANDLER(command_parse_str_to_buf, reg_value, buf, reg->size);
 		if (retval != ERROR_OK) {
 			free(buf);
 			return retval;
diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h
index 495da2a..8391a96 100644
--- a/src/target/xtensa/xtensa_debug_module.h
+++ b/src/target/xtensa/xtensa_debug_module.h
@@ -75,6 +75,7 @@ enum xtensa_dm_reg {
 	XDMREG_DELAYCNT,
 	XDMREG_MEMADDRSTART,
 	XDMREG_MEMADDREND,
+	XDMREG_DEBUGPC,/*Unsupported, undocumented, may not be present*/
 	XDMREG_EXTTIMELO,
 	XDMREG_EXTTIMEHI,
 	XDMREG_TRAXRSVD48,
@@ -184,6 +185,7 @@ struct xtensa_dm_reg_offsets {
 	{ .nar = 0x07, .apb = 0x001c },	/* XDMREG_DELAYCNT */		\
 	{ .nar = 0x08, .apb = 0x0020 },	/* XDMREG_MEMADDRSTART */	\
 	{ .nar = 0x09, .apb = 0x0024 },	/* XDMREG_MEMADDREND */		\
+	{ .nar = 0x0f, .apb = 0x003c },	/* XDMREG_DEBUGPC */		\
 	{ .nar = 0x10, .apb = 0x0040 },	/* XDMREG_EXTTIMELO */		\
 	{ .nar = 0x11, .apb = 0x0044 },	/* XDMREG_EXTTIMEHI */		\
 	{ .nar = 0x12, .apb = 0x0048 },	/* XDMREG_TRAXRSVD48 */		\
diff --git a/tcl/board/digilent_anvyl.cfg b/tcl/board/digilent_anvyl.cfg
new file mode 100644
index 0000000..e820028
--- /dev/null
+++ b/tcl/board/digilent_anvyl.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Anvyl with Xilinx Spartan-6 FPGA
+# https://digilent.com/reference/programmable-logic/anvyl/start
+# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1
+# adapter.
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is the JTAG channel
+# channel 1 is a user serial channel to pins on the FPGA
+ftdi channel 0
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/nxp_imx8mp-evk.cfg b/tcl/board/nxp_imx8mp-evk.cfg
new file mode 100644
index 0000000..4e101d4
--- /dev/null
+++ b/tcl/board/nxp_imx8mp-evk.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP IMX8M Plus EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+
+# board has an i.MX8MP with 4 Cortex-A55 cores
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8mp.cfg]
diff --git a/tcl/board/ti_cc26x2x7_launchpad.cfg b/tcl/board/ti_cc26x2x7_launchpad.cfg
new file mode 100644
index 0000000..9e6e72e
--- /dev/null
+++ b/tcl/board/ti_cc26x2x7_launchpad.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC1352P7 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2x7.cfg]
diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 92b2605..862c4aa 100644
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -35,7 +35,7 @@ set XC6S_JSTART 0x0c
 set XC6S_BYPASS 0x3f
 
 proc xc6s_program {tap} {
-	echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program'"
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program'"
 	global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
 	irscan $tap $XC6S_JSHUTDOWN
 	irscan $tap $XC6S_JPROGRAM
@@ -45,7 +45,7 @@ proc xc6s_program {tap} {
 
 #xtp038 and xc3sprog approach
 proc xc6s_program_iprog {tap} {
-	echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program_iprog'"
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program_iprog'"
 	global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
 	irscan $tap $XC6S_JSHUTDOWN
 	runtest 16
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index f5b0733..6f8f4ae 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -49,7 +49,7 @@ set XC7_JSTART 0x0c
 set XC7_BYPASS 0x3f
 
 proc xc7_program {tap} {
-	echo "DEPRECATED! use 'virtex2 program ...' not 'xc7_program'"
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc7_program'"
 	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
 	irscan $tap $XC7_JSHUTDOWN
 	irscan $tap $XC7_JPROGRAM
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 4d7f26c..63a67da 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -109,7 +109,7 @@ set XCU_JSTART 0x0c
 set XCU_BYPASS 0x3f
 
 proc xcu_program {tap} {
-	echo "DEPRECATED! use 'virtex2 program ...' not 'xcu_program'"
+	echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xcu_program'"
 	global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
 	irscan $tap $XCU_JSHUTDOWN
 	irscan $tap $XCU_JPROGRAM
diff --git a/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg
new file mode 100644
index 0000000..8a804ec
--- /dev/null
+++ b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Sipeed USB-JTAG/TTL RISC-V Debugger
+#
+# https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html
+#
+
+adapter driver ftdi
+ftdi device_desc "Dual RS232"
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+# Every pin set as high impedance except TCK, TDI, TDO, TMS and RST
+ftdi layout_init 0x0028 0x002b
+
+transport select jtag
+
+# nSRST defined on pin RST of the Debugger (pin ADBUS5 [AD5] on the FT2232D chip)
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/tcl/target/imx8mp.cfg b/tcl/target/imx8mp.cfg
new file mode 100644
index 0000000..bddbcfd
--- /dev/null
+++ b/tcl/target/imx8mp.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for NXP i.MX8M Plus SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx8m
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core
+}
+
+# declare the auxiliary Cortex-M7 core on AP #4
+target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A53 core 0
+targets $_TARGETNAME.0
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 8dc0e7a..73b3003 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -159,6 +159,7 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
 proc setup_crx {core_name dbgbase ctibase num boot} {
 	global _CHIPNAME
 	global _DAPNAME
+	global _targets
 	for { set _core 0 } { $_core < $num } { incr _core } {
 		set _TARGETNAME $_CHIPNAME.$core_name
 		set _CTINAME $_TARGETNAME.cti
diff --git a/tcl/target/spacemit-k1.cfg b/tcl/target/spacemit-k1.cfg
new file mode 100644
index 0000000..ef5d783
--- /dev/null
+++ b/tcl/target/spacemit-k1.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SpacemiT Key Stone K1 target
+#
+# https://www.spacemit.com/key-stone-k1
+#
+
+transport select jtag
+
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME k1
+}
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    set _cores 1
+}
+
+if { [info exists SECJTAG] } {
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21
+} else {
+    jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+    jtag configure pre.unknown -event tap-enable ""
+
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable
+    jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+    jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+    jtag configure post.unknown -event setup {
+        global _CHIPNAME
+
+        irscan post.unknown 0x98
+        drscan post.unknown 16 0xa
+
+        jtag tapenable pre.unknown
+        jtag tapenable $_CHIPNAME.cpu
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+set DBGBASE {0x0 0x400}
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
+        -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
+
+    if { [expr {$_core % 4}] == 0 } {
+        $_TARGETNAME.$_core configure -rtos hwthread
+    }
+
+    set _smp_command "$_smp_command $_TARGETNAME.$_core"
+}
+
+eval $_smp_command
+
+set _SPEED 8000
+
+$_TARGETNAME.0 configure -event examine-start {
+    adapter speed $_SPEED
+    puts [ adapter speed ]
+}
+
+foreach t [target names] {
+    # $t riscv set_mem_access sysbus progbuf
+    $t riscv set_mem_access progbuf
+}
diff --git a/tcl/target/ti_cc26x2x7.cfg b/tcl/target/ti_cc26x2x7.cfg
new file mode 100644
index 0000000..91c1a80
--- /dev/null
+++ b/tcl/target/ti_cc26x2x7.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2x7
+set JRC_TAPID 0x1BB7702F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]
diff --git a/tools/scripts/checkpatch.pl b/tools/scripts/checkpatch.pl
index 26589be..59a3eed 100755
--- a/tools/scripts/checkpatch.pl
+++ b/tools/scripts/checkpatch.pl
@@ -2384,6 +2384,10 @@ sub show_type {
 sub report {
 	my ($level, $type, $msg) = @_;
 
+	# OpenOCD specific: Begin: Flatten ERROR, WARNING and CHECK as ERROR
+	$level = 'ERROR';
+	# OpenOCD specific: End
+
 	if (!show_type($type) ||
 	    (defined $tst_only && $msg !~ /\Q$tst_only\E/)) {
 		return 0;
@@ -3726,6 +3730,8 @@ sub process {
 				# OpenOCD specific: Begin
 				} elsif ($realfile =~ /\.(am|cfg|tcl)$/) {
 					$comment = '#';
+				} elsif ($realfile =~ /\.(ld)$/) {
+					$comment = '/*';
 				# OpenOCD specific: End
 				}
 
@@ -7638,9 +7644,15 @@ sub process {
 	print report_dump();
 	if ($summary && !($clean == 1 && $quiet == 1)) {
 		print "$filename " if ($summary_file);
+		if (!$OpenOCD) {
 		print "total: $cnt_error errors, $cnt_warn warnings, " .
 			(($check)? "$cnt_chk checks, " : "") .
 			"$cnt_lines lines checked\n";
+		} # $OpenOCD
+		# OpenOCD specific: Begin: Report total as errors
+		my $total = $cnt_error + $cnt_warn + $cnt_chk;
+		print "total: $total errors, $cnt_lines lines checked\n";
+		# OpenOCD specific: End
 	}
 
 	if ($quiet == 0) {