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| author | Adrian Negreanu <adrian.negreanu@nxp.com> | 2020-11-20 18:53:51 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-03-10 21:31:27 +0000 |
| commit | 169e5bf1862ab52c4ba28a26f15124293d2bf443 (patch) | |
| tree | 202384cbe5cf0f6b509c9d3876aae611e8c18ab6 | |
| parent | fa76e036b92b22e07c9e7b70fa9c4cf504170a45 (diff) | |
| download | riscv-openocd-169e5bf1862ab52c4ba28a26f15124293d2bf443.zip riscv-openocd-169e5bf1862ab52c4ba28a26f15124293d2bf443.tar.gz riscv-openocd-169e5bf1862ab52c4ba28a26f15124293d2bf443.tar.bz2 | |
armv7m_trace_itm_config: wait for ITMBusy to be cleared
pg315 of CoreSight Components:
It is recommended that the ITMEn bit is cleared and waits for the
ITMBusy bit to be cleared, before changing any fields in the
Control Register, otherwise the behavior can be unpredictable.
Change-Id: Ie9a2b842825c98ee5edc9a35776320c668047769
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/6043
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/armv7m_trace.c | 28 | ||||
| -rw-r--r-- | src/target/cortex_m.h | 2 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c index 10f1422..32b48a7 100644 --- a/src/target/armv7m_trace.c +++ b/src/target/armv7m_trace.c @@ -24,6 +24,7 @@ #include <target/cortex_m.h> #include <target/armv7m_trace.h> #include <jtag/interface.h> +#include <helper/time_support.h> #define TRACE_BUF_SIZE 4096 @@ -162,6 +163,33 @@ int armv7m_trace_itm_config(struct target *target) if (retval != ERROR_OK) return retval; + /* pg315 of CoreSight Components + * It is recommended that the ITMEn bit is cleared and waits for the + * ITMBusy bit to be cleared, before changing any fields in the + * Control Register, otherwise the behavior can be unpredictable. + */ + uint32_t itm_tcr; + retval = target_read_u32(target, ITM_TCR, &itm_tcr); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, + ITM_TCR, + itm_tcr & ~ITM_TCR_ITMENA_BIT + ); + if (retval != ERROR_OK) + return retval; + + int64_t then = timeval_ms() + 1000; + do { + retval = target_read_u32(target, ITM_TCR, &itm_tcr); + if (retval != ERROR_OK) + return retval; + if (timeval_ms() > then) { + LOG_ERROR("timeout waiting for ITM_TCR_BUSY_BIT"); + return ERROR_FAIL; + } + } while (itm_tcr & ITM_TCR_BUSY_BIT); + /* Enable ITM, TXENA, set TraceBusID and other parameters */ retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) | (trace_config->itm_diff_timestamps << 1) | diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index b470fbd..1e2197b 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -35,6 +35,8 @@ #define ITM_TER0 0xE0000E00 #define ITM_TPR 0xE0000E40 #define ITM_TCR 0xE0000E80 +#define ITM_TCR_ITMENA_BIT BIT(0) +#define ITM_TCR_BUSY_BIT BIT(23) #define ITM_LAR 0xE0000FB0 #define ITM_LAR_KEY 0xC5ACCE55 |