Merge pull request #815 from riscv/s_aia

target/riscv: Expose S?aia CSRs if they're on the target.

5 files changed, 250 insertions, 96 deletions

diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index c2da4e6..3ac537c 100644
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-/* Copyright (c) 2022 RISC-V International */
+/* Copyright (c) 2023 RISC-V International */
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (dcdf8d3)
+ * https://github.com/riscv/riscv-opcodes (ed68c21)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -156,14 +156,17 @@
 #define MENVCFG_CBIE  0x00000030
 #define MENVCFG_CBCFE 0x00000040
 #define MENVCFG_CBZE  0x00000080
+#define MENVCFG_HADE  0x2000000000000000
 #define MENVCFG_PBMTE 0x4000000000000000
 #define MENVCFG_STCE  0x8000000000000000
 
+#define MENVCFGH_HADE  0x20000000
 #define MENVCFGH_PBMTE 0x40000000
 #define MENVCFGH_STCE  0x80000000
 
 #define MSTATEEN0_CS       0x00000001
 #define MSTATEEN0_FCSR     0x00000002
+#define MSTATEEN0_JVT      0x00000004
 #define MSTATEEN0_HCONTEXT 0x0200000000000000
 #define MSTATEEN0_HENVCFG  0x4000000000000000
 #define MSTATEEN_HSTATEEN  0x8000000000000000
@@ -190,14 +193,17 @@
 #define HENVCFG_CBIE  0x00000030
 #define HENVCFG_CBCFE 0x00000040
 #define HENVCFG_CBZE  0x00000080
+#define HENVCFG_HADE  0x2000000000000000
 #define HENVCFG_PBMTE 0x4000000000000000
 #define HENVCFG_STCE  0x8000000000000000
 
+#define HENVCFGH_HADE  0x20000000
 #define HENVCFGH_PBMTE 0x40000000
 #define HENVCFGH_STCE  0x80000000
 
 #define HSTATEEN0_CS       0x00000001
 #define HSTATEEN0_FCSR     0x00000002
+#define HSTATEEN0_JVT      0x00000004
 #define HSTATEEN0_SCONTEXT 0x0200000000000000
 #define HSTATEEN0_SENVCFG  0x4000000000000000
 #define HSTATEEN_SSTATEEN  0x8000000000000000
@@ -213,6 +219,7 @@
 
 #define SSTATEEN0_CS   0x00000001
 #define SSTATEEN0_FCSR 0x00000002
+#define SSTATEEN0_JVT  0x00000004
 
 #define MSECCFG_MML    0x00000001
 #define MSECCFG_MMWP   0x00000002
@@ -220,6 +227,10 @@
 #define MSECCFG_USEED  0x00000100
 #define MSECCFG_SSEED  0x00000200
 
+/* jvt fields */
+#define JVT_MODE   0x3F
+#define JVT_BASE   (~0x3F)
+
 #define PRV_U 0
 #define PRV_S 1
 #define PRV_M 3
@@ -366,12 +377,8 @@
 #define MASK_ADD8 0xfe00707f
 #define MATCH_ADD_UW 0x800003b
 #define MASK_ADD_UW 0xfe00707f
-#define MATCH_ADDD 0x7b
-#define MASK_ADDD 0xfe00707f
 #define MATCH_ADDI 0x13
 #define MASK_ADDI 0x707f
-#define MATCH_ADDID 0x5b
-#define MASK_ADDID 0x707f
 #define MATCH_ADDIW 0x1b
 #define MASK_ADDIW 0x707f
 #define MATCH_ADDW 0x3b
@@ -474,10 +481,6 @@
 #define MASK_BINV 0xfe00707f
 #define MATCH_BINVI 0x68001013
 #define MASK_BINVI 0xfc00707f
-#define MATCH_BITREV 0xe6000077
-#define MASK_BITREV 0xfe00707f
-#define MATCH_BITREVI 0xe8000077
-#define MASK_BITREVI 0xfc00707f
 #define MATCH_BLT 0x4063
 #define MASK_BLT 0x707f
 #define MATCH_BLTU 0x6063
@@ -490,8 +493,6 @@
 #define MASK_BMATXOR 0xfe00707f
 #define MATCH_BNE 0x1063
 #define MASK_BNE 0x707f
-#define MATCH_BPICK 0x3077
-#define MASK_BPICK 0x600707f
 #define MATCH_BSET 0x28001033
 #define MASK_BSET 0xfe00707f
 #define MATCH_BSETI 0x28001013
@@ -542,38 +543,48 @@
 #define MASK_C_JALR 0xf07f
 #define MATCH_C_JR 0x8002
 #define MASK_C_JR 0xf07f
+#define MATCH_C_LBU 0x8000
+#define MASK_C_LBU 0xfc03
 #define MATCH_C_LD 0x6000
 #define MASK_C_LD 0xe003
 #define MATCH_C_LDSP 0x6002
 #define MASK_C_LDSP 0xe003
+#define MATCH_C_LH 0x8440
+#define MASK_C_LH 0xfc43
+#define MATCH_C_LHU 0x8400
+#define MASK_C_LHU 0xfc43
 #define MATCH_C_LI 0x4001
 #define MASK_C_LI 0xe003
-#define MATCH_C_LQ 0x2000
-#define MASK_C_LQ 0xe003
-#define MATCH_C_LQSP 0x2002
-#define MASK_C_LQSP 0xe003
 #define MATCH_C_LUI 0x6001
 #define MASK_C_LUI 0xe003
 #define MATCH_C_LW 0x4000
 #define MASK_C_LW 0xe003
 #define MATCH_C_LWSP 0x4002
 #define MASK_C_LWSP 0xe003
+#define MATCH_C_MUL 0x9c41
+#define MASK_C_MUL 0xfc63
 #define MATCH_C_MV 0x8002
 #define MASK_C_MV 0xf003
 #define MATCH_C_NOP 0x1
 #define MASK_C_NOP 0xef83
+#define MATCH_C_NOT 0x9c75
+#define MASK_C_NOT 0xfc7f
 #define MATCH_C_OR 0x8c41
 #define MASK_C_OR 0xfc63
+#define MATCH_C_SB 0x8800
+#define MASK_C_SB 0xfc03
 #define MATCH_C_SD 0xe000
 #define MASK_C_SD 0xe003
 #define MATCH_C_SDSP 0xe002
 #define MASK_C_SDSP 0xe003
+#define MATCH_C_SEXT_B 0x9c65
+#define MASK_C_SEXT_B 0xfc7f
+#define MATCH_C_SEXT_H 0x9c6d
+#define MASK_C_SEXT_H 0xfc7f
+#define MATCH_C_SH 0x8c00
+#define MASK_C_SH 0xfc43
 #define MATCH_C_SLLI 0x2
 #define MASK_C_SLLI 0xe003
-#define MATCH_C_SQ 0xa000
-#define MASK_C_SQ 0xe003
-#define MATCH_C_SQSP 0xa002
-#define MASK_C_SQSP 0xe003
 #define MATCH_C_SRAI 0x8401
 #define MASK_C_SRAI 0xec03
 #define MATCH_C_SRLI 0x8001
@@ -588,6 +599,12 @@
 #define MASK_C_SWSP 0xe003
 #define MATCH_C_XOR 0x8c21
 #define MASK_C_XOR 0xfc63
+#define MATCH_C_ZEXT_B 0x9c61
+#define MASK_C_ZEXT_B 0xfc7f
+#define MATCH_C_ZEXT_H 0x9c69
+#define MASK_C_ZEXT_H 0xfc7f
+#define MATCH_C_ZEXT_W 0x9c71
+#define MASK_C_ZEXT_W 0xfc7f
 #define MATCH_CBO_CLEAN 0x10200f
 #define MASK_CBO_CLEAN 0xfff07fff
 #define MATCH_CBO_FLUSH 0x20200f
@@ -602,12 +619,6 @@
 #define MASK_CLMULH 0xfe00707f
 #define MATCH_CLMULR 0xa002033
 #define MASK_CLMULR 0xfe00707f
-#define MATCH_CLO16 0xaeb00077
-#define MASK_CLO16 0xfff0707f
-#define MATCH_CLO32 0xafb00077
-#define MASK_CLO32 0xfff0707f
-#define MATCH_CLO8 0xae300077
-#define MASK_CLO8 0xfff0707f
 #define MATCH_CLRS16 0xae800077
 #define MASK_CLRS16 0xfff0707f
 #define MATCH_CLRS32 0xaf800077
@@ -624,6 +635,20 @@
 #define MASK_CLZ8 0xfff0707f
 #define MATCH_CLZW 0x6000101b
 #define MASK_CLZW 0xfff0707f
+#define MATCH_CM_JALT 0xa002
+#define MASK_CM_JALT 0xfc03
+#define MATCH_CM_MVA01S 0xac62
+#define MASK_CM_MVA01S 0xfc63
+#define MATCH_CM_MVSA01 0xac22
+#define MASK_CM_MVSA01 0xfc63
+#define MATCH_CM_POP 0xba02
+#define MASK_CM_POP 0xff03
+#define MATCH_CM_POPRET 0xbe02
+#define MASK_CM_POPRET 0xff03
+#define MATCH_CM_POPRETZ 0xbc02
+#define MASK_CM_POPRETZ 0xff03
+#define MATCH_CM_PUSH 0xb802
+#define MASK_CM_PUSH 0xff03
 #define MATCH_CMIX 0x6001033
 #define MASK_CMIX 0x600707f
 #define MATCH_CMOV 0x6005033
@@ -676,6 +701,10 @@
 #define MASK_CTZ 0xfff0707f
 #define MATCH_CTZW 0x6010101b
 #define MASK_CTZW 0xfff0707f
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
 #define MATCH_DIV 0x2004033
 #define MASK_DIV 0xfe00707f
 #define MATCH_DIVU 0x2005033
@@ -1238,14 +1267,10 @@
 #define MASK_LBU 0x707f
 #define MATCH_LD 0x3003
 #define MASK_LD 0x707f
-#define MATCH_LDU 0x7003
-#define MASK_LDU 0x707f
 #define MATCH_LH 0x1003
 #define MASK_LH 0x707f
 #define MATCH_LHU 0x5003
 #define MASK_LHU 0x707f
-#define MATCH_LQ 0x300f
-#define MASK_LQ 0x707f
 #define MATCH_LR_D 0x1000302f
 #define MASK_LR_D 0xf9f0707f
 #define MATCH_LR_W 0x1000202f
@@ -1262,14 +1287,10 @@
 #define MASK_MAX 0xfe00707f
 #define MATCH_MAXU 0xa007033
 #define MASK_MAXU 0xfe00707f
-#define MATCH_MAXW 0xf2000077
-#define MASK_MAXW 0xfe00707f
 #define MATCH_MIN 0xa004033
 #define MASK_MIN 0xfe00707f
 #define MATCH_MINU 0xa005033
 #define MASK_MINU 0xfe00707f
-#define MATCH_MINW 0xf0000077
-#define MASK_MINW 0xfe00707f
 #define MATCH_MRET 0x30200073
 #define MASK_MRET 0xffffffff
 #define MATCH_MSUBR32 0xc6001077
@@ -1312,8 +1333,6 @@
 #define MASK_PBSADA 0xfe00707f
 #define MATCH_PKBB16 0xe001077
 #define MASK_PKBB16 0xfe00707f
-#define MATCH_PKBB32 0xe002077
-#define MASK_PKBB32 0xfe00707f
 #define MATCH_PKBT16 0x1e001077
 #define MASK_PKBT16 0xfe00707f
 #define MATCH_PKBT32 0x1e002077
@@ -1324,8 +1343,6 @@
 #define MASK_PKTB32 0xfe00707f
 #define MATCH_PKTT16 0x2e001077
 #define MASK_PKTT16 0xfe00707f
-#define MATCH_PKTT32 0x2e002077
-#define MASK_PKTT32 0xfe00707f
 #define MATCH_PREFETCH_I 0x6013
 #define MASK_PREFETCH_I 0x1f07fff
 #define MATCH_PREFETCH_R 0x106013
@@ -1478,20 +1495,18 @@
 #define MASK_SLL32 0xfe00707f
 #define MATCH_SLL8 0x5c000077
 #define MASK_SLL8 0xfe00707f
-#define MATCH_SLLD 0x107b
-#define MASK_SLLD 0xfe00707f
 #define MATCH_SLLI 0x1013
-#define MASK_SLLI 0xf800707f
+#define MASK_SLLI 0xfc00707f
 #define MATCH_SLLI16 0x74000077
 #define MASK_SLLI16 0xff00707f
 #define MATCH_SLLI32 0x74002077
 #define MASK_SLLI32 0xfe00707f
 #define MATCH_SLLI8 0x7c000077
 #define MASK_SLLI8 0xff80707f
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32 0xfe00707f
 #define MATCH_SLLI_UW 0x800101b
 #define MASK_SLLI_UW 0xfc00707f
-#define MATCH_SLLID 0x105b
-#define MASK_SLLID 0xfc00707f
 #define MATCH_SLLIW 0x101b
 #define MASK_SLLIW 0xfe00707f
 #define MATCH_SLLW 0x103b
@@ -1604,8 +1619,6 @@
 #define MASK_SMXDS 0xfe00707f
 #define MATCH_SMXDS32 0x78002077
 #define MASK_SMXDS32 0xfe00707f
-#define MATCH_SQ 0x4023
-#define MASK_SQ 0x707f
 #define MATCH_SRA 0x40005033
 #define MASK_SRA 0xfe00707f
 #define MATCH_SRA16 0x50000077
@@ -1622,10 +1635,8 @@
 #define MASK_SRA8_U 0xfe00707f
 #define MATCH_SRA_U 0x24001077
 #define MASK_SRA_U 0xfe00707f
-#define MATCH_SRAD 0x4000507b
-#define MASK_SRAD 0xfe00707f
 #define MATCH_SRAI 0x40005013
-#define MASK_SRAI 0xf800707f
+#define MASK_SRAI 0xfc00707f
 #define MATCH_SRAI16 0x70000077
 #define MASK_SRAI16 0xff00707f
 #define MATCH_SRAI16_U 0x71000077
@@ -1638,10 +1649,10 @@
 #define MASK_SRAI8 0xff80707f
 #define MATCH_SRAI8_U 0x78800077
 #define MASK_SRAI8_U 0xff80707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32 0xfe00707f
 #define MATCH_SRAI_U 0xd4001077
 #define MASK_SRAI_U 0xfc00707f
-#define MATCH_SRAID 0x4000505b
-#define MASK_SRAID 0xfc00707f
 #define MATCH_SRAIW 0x4000501b
 #define MASK_SRAIW 0xfe00707f
 #define MATCH_SRAIW_U 0x34001077
@@ -1664,10 +1675,8 @@
 #define MASK_SRL8 0xfe00707f
 #define MATCH_SRL8_U 0x6a000077
 #define MASK_SRL8_U 0xfe00707f
-#define MATCH_SRLD 0x507b
-#define MASK_SRLD 0xfe00707f
 #define MATCH_SRLI 0x5013
-#define MASK_SRLI 0xf800707f
+#define MASK_SRLI 0xfc00707f
 #define MATCH_SRLI16 0x72000077
 #define MASK_SRLI16 0xff00707f
 #define MATCH_SRLI16_U 0x73000077
@@ -1680,8 +1689,8 @@
 #define MASK_SRLI8 0xff80707f
 #define MATCH_SRLI8_U 0x7a800077
 #define MASK_SRLI8_U 0xff80707f
-#define MATCH_SRLID 0x505b
-#define MASK_SRLID 0xfc00707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32 0xfe00707f
 #define MATCH_SRLIW 0x501b
 #define MASK_SRLIW 0xfe00707f
 #define MATCH_SRLW 0x503b
@@ -1712,8 +1721,6 @@
 #define MASK_SUB64 0xfe00707f
 #define MATCH_SUB8 0x4a000077
 #define MASK_SUB8 0xfe00707f
-#define MATCH_SUBD 0x4000007b
-#define MASK_SUBD 0xfe00707f
 #define MATCH_SUBW 0x4000003b
 #define MASK_SUBW 0xfe00707f
 #define MATCH_SUNPKD810 0xac800077
@@ -1728,8 +1735,6 @@
 #define MASK_SUNPKD832 0xfff0707f
 #define MATCH_SW 0x2023
 #define MASK_SW 0x707f
-#define MATCH_SWAP8 0xad800077
-#define MASK_SWAP8 0xfff0707f
 #define MATCH_UCLIP16 0x85000077
 #define MASK_UCLIP16 0xff00707f
 #define MATCH_UCLIP32 0xf4000077
@@ -2750,10 +2755,6 @@
 #define MASK_VZEXT_VF4 0xfc0ff07f
 #define MATCH_VZEXT_VF8 0x48012057
 #define MASK_VZEXT_VF8 0xfc0ff07f
-#define MATCH_WEXT 0xce000077
-#define MASK_WEXT 0xfe00707f
-#define MATCH_WEXTI 0xde000077
-#define MASK_WEXTI 0xfe00707f
 #define MATCH_WFI 0x10500073
 #define MASK_WFI 0xffffffff
 #define MATCH_WRS_NTO 0xd00073
@@ -2793,6 +2794,7 @@
 #define CSR_VXRM 0xa
 #define CSR_VCSR 0xf
 #define CSR_SEED 0x15
+#define CSR_JVT 0x17
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
@@ -2845,6 +2847,9 @@
 #define CSR_STVAL 0x143
 #define CSR_SIP 0x144
 #define CSR_STIMECMP 0x14d
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+#define CSR_STOPEI 0x15c
 #define CSR_SATP 0x180
 #define CSR_SCONTEXT 0x5a8
 #define CSR_VSSTATUS 0x200
@@ -2856,6 +2861,9 @@
 #define CSR_VSTVAL 0x243
 #define CSR_VSIP 0x244
 #define CSR_VSTIMECMP 0x24d
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+#define CSR_VSTOPEI 0x25c
 #define CSR_VSATP 0x280
 #define CSR_HSTATUS 0x600
 #define CSR_HEDELEG 0x602
@@ -2864,6 +2872,8 @@
 #define CSR_HTIMEDELTA 0x605
 #define CSR_HCOUNTEREN 0x606
 #define CSR_HGEIE 0x607
+#define CSR_HVIEN 0x608
+#define CSR_HVICTL 0x609
 #define CSR_HENVCFG 0x60a
 #define CSR_HSTATEEN0 0x60c
 #define CSR_HSTATEEN1 0x60d
@@ -2872,11 +2882,15 @@
 #define CSR_HTVAL 0x643
 #define CSR_HIP 0x644
 #define CSR_HVIP 0x645
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
 #define CSR_HTINST 0x64a
 #define CSR_HGATP 0x680
 #define CSR_HCONTEXT 0x6a8
 #define CSR_HGEIP 0xe12
+#define CSR_VSTOPI 0xeb0
 #define CSR_SCOUNTOVF 0xda0
+#define CSR_STOPI 0xdb0
 #define CSR_UTVT 0x7
 #define CSR_UNXTI 0x45
 #define CSR_UINTSTATUS 0x46
@@ -2899,6 +2913,8 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
 #define CSR_MENVCFG 0x30a
 #define CSR_MSTATEEN0 0x30c
 #define CSR_MSTATEEN1 0x30d
@@ -2912,6 +2928,9 @@
 #define CSR_MIP 0x344
 #define CSR_MTINST 0x34a
 #define CSR_MTVAL2 0x34b
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+#define CSR_MTOPEI 0x35c
 #define CSR_PMPCFG0 0x3a0
 #define CSR_PMPCFG1 0x3a1
 #define CSR_PMPCFG2 0x3a2
@@ -3070,10 +3089,20 @@
 #define CSR_MIMPID 0xf13
 #define CSR_MHARTID 0xf14
 #define CSR_MCONFIGPTR 0xf15
+#define CSR_MTOPI 0xfb0
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
 #define CSR_STIMECMPH 0x15d
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
 #define CSR_VSTIMECMPH 0x25d
 #define CSR_HTIMEDELTAH 0x615
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
 #define CSR_HENVCFGH 0x61a
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
 #define CSR_HSTATEEN0H 0x61c
 #define CSR_HSTATEEN1H 0x61d
 #define CSR_HSTATEEN2H 0x61e
@@ -3111,11 +3140,16 @@
 #define CSR_HPMCOUNTER30H 0xc9e
 #define CSR_HPMCOUNTER31H 0xc9f
 #define CSR_MSTATUSH 0x310
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
 #define CSR_MENVCFGH 0x31a
 #define CSR_MSTATEEN0H 0x31c
 #define CSR_MSTATEEN1H 0x31d
 #define CSR_MSTATEEN2H 0x31e
 #define CSR_MSTATEEN3H 0x31f
+#define CSR_MIPH 0x354
 #define CSR_MHPMEVENT3H 0x723
 #define CSR_MHPMEVENT4H 0x724
 #define CSR_MHPMEVENT5H 0x725
@@ -3221,7 +3255,7 @@
 #define INSN_FIELD_IMM12LO 0xf80
 #define INSN_FIELD_BIMM12LO 0xf80
 #define INSN_FIELD_ZIMM 0xf8000
-#define INSN_FIELD_SHAMT 0x7f00000
+#define INSN_FIELD_SHAMTQ 0x7f00000
 #define INSN_FIELD_SHAMTW 0x1f00000
 #define INSN_FIELD_SHAMTW4 0xf00000
 #define INSN_FIELD_SHAMTD 0x3f00000
@@ -3276,6 +3310,11 @@
 #define INSN_FIELD_C_UIMM9SPHI 0x1000
 #define INSN_FIELD_C_UIMM10SP_S 0x1f80
 #define INSN_FIELD_C_UIMM9SP_S 0x1f80
+#define INSN_FIELD_C_UIMM2 0x60
+#define INSN_FIELD_C_UIMM1 0x20
+#define INSN_FIELD_C_RLIST 0xf0
+#define INSN_FIELD_C_SPIMM 0xc
+#define INSN_FIELD_C_INDEX 0x3fc
 #define INSN_FIELD_RS1_P 0x380
 #define INSN_FIELD_RS2_P 0x1c
 #define INSN_FIELD_RD_P 0x1c
@@ -3288,6 +3327,8 @@
 #define INSN_FIELD_C_RS2_N0 0x7c
 #define INSN_FIELD_C_RS1_N0 0xf80
 #define INSN_FIELD_C_RS2 0x7c
+#define INSN_FIELD_C_SREG1 0x380
+#define INSN_FIELD_C_SREG2 0x1c
 #endif
 #ifdef DECLARE_INSN
 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
@@ -3296,9 +3337,7 @@ DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32)
 DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64)
 DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8)
 DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
-DECLARE_INSN(addd, MATCH_ADDD, MASK_ADDD)
 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-DECLARE_INSN(addid, MATCH_ADDID, MASK_ADDID)
 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
 DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI)
@@ -3350,15 +3389,12 @@ DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
 DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
 DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
-DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV)
-DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
 DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
 DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK)
 DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
 DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
@@ -3384,22 +3420,27 @@ DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU)
 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
+DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
-DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL)
 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT)
 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B)
+DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H)
+DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
-DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
@@ -3407,6 +3448,9 @@ DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B)
+DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H)
+DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W)
 DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN)
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH)
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL)
@@ -3414,9 +3458,6 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO)
 DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
 DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
 DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
-DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16)
-DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32)
-DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8)
 DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16)
 DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32)
 DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8)
@@ -3425,6 +3466,13 @@ DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16)
 DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32)
 DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8)
 DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
+DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
+DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01)
+DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
+DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET)
+DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ)
+DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
 DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
 DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
 DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16)
@@ -3451,6 +3499,8 @@ DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
 DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
@@ -3732,10 +3782,8 @@ DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U)
 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU)
 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-DECLARE_INSN(lq, MATCH_LQ, MASK_LQ)
 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
@@ -3744,10 +3792,8 @@ DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32)
 DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
 DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
-DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW)
 DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
 DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
-DECLARE_INSN(minw, MATCH_MINW, MASK_MINW)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32)
 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
@@ -3769,13 +3815,11 @@ DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
 DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD)
 DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA)
 DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16)
-DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32)
 DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16)
 DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32)
 DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16)
 DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32)
 DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16)
-DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32)
 DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I)
 DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R)
 DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W)
@@ -3852,13 +3896,12 @@ DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
 DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16)
 DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32)
 DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8)
-DECLARE_INSN(slld, MATCH_SLLD, MASK_SLLD)
 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16)
 DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32)
 DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8)
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
 DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
-DECLARE_INSN(sllid, MATCH_SLLID, MASK_SLLID)
 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
@@ -3915,7 +3958,6 @@ DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16)
 DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8)
 DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS)
 DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32)
-DECLARE_INSN(sq, MATCH_SQ, MASK_SQ)
 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16)
 DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U)
@@ -3924,7 +3966,6 @@ DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U)
 DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8)
 DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U)
 DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U)
-DECLARE_INSN(srad, MATCH_SRAD, MASK_SRAD)
 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16)
 DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U)
@@ -3932,8 +3973,8 @@ DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32)
 DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U)
 DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8)
 DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
 DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U)
-DECLARE_INSN(sraid, MATCH_SRAID, MASK_SRAID)
 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U)
 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
@@ -3945,7 +3986,6 @@ DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32)
 DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U)
 DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8)
 DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U)
-DECLARE_INSN(srld, MATCH_SRLD, MASK_SRLD)
 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
 DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16)
 DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U)
@@ -3953,7 +3993,7 @@ DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32)
 DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U)
 DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8)
 DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U)
-DECLARE_INSN(srlid, MATCH_SRLID, MASK_SRLID)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
@@ -3969,7 +4009,6 @@ DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16)
 DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32)
 DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64)
 DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8)
-DECLARE_INSN(subd, MATCH_SUBD, MASK_SUBD)
 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
 DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810)
 DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820)
@@ -3977,7 +4016,6 @@ DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830)
 DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831)
 DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832)
 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8)
 DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16)
 DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32)
 DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8)
@@ -4488,8 +4526,6 @@ DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
 DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
 DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
 DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8)
-DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT)
-DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI)
 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
@@ -4515,6 +4551,7 @@ DECLARE_CSR(vxsat, CSR_VXSAT)
 DECLARE_CSR(vxrm, CSR_VXRM)
 DECLARE_CSR(vcsr, CSR_VCSR)
 DECLARE_CSR(seed, CSR_SEED)
+DECLARE_CSR(jvt, CSR_JVT)
 DECLARE_CSR(cycle, CSR_CYCLE)
 DECLARE_CSR(time, CSR_TIME)
 DECLARE_CSR(instret, CSR_INSTRET)
@@ -4567,6 +4604,9 @@ DECLARE_CSR(scause, CSR_SCAUSE)
 DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(stimecmp, CSR_STIMECMP)
+DECLARE_CSR(siselect, CSR_SISELECT)
+DECLARE_CSR(sireg, CSR_SIREG)
+DECLARE_CSR(stopei, CSR_STOPEI)
 DECLARE_CSR(satp, CSR_SATP)
 DECLARE_CSR(scontext, CSR_SCONTEXT)
 DECLARE_CSR(vsstatus, CSR_VSSTATUS)
@@ -4578,6 +4618,9 @@ DECLARE_CSR(vscause, CSR_VSCAUSE)
 DECLARE_CSR(vstval, CSR_VSTVAL)
 DECLARE_CSR(vsip, CSR_VSIP)
 DECLARE_CSR(vstimecmp, CSR_VSTIMECMP)
+DECLARE_CSR(vsiselect, CSR_VSISELECT)
+DECLARE_CSR(vsireg, CSR_VSIREG)
+DECLARE_CSR(vstopei, CSR_VSTOPEI)
 DECLARE_CSR(vsatp, CSR_VSATP)
 DECLARE_CSR(hstatus, CSR_HSTATUS)
 DECLARE_CSR(hedeleg, CSR_HEDELEG)
@@ -4586,6 +4629,8 @@ DECLARE_CSR(hie, CSR_HIE)
 DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
 DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
 DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(hvien, CSR_HVIEN)
+DECLARE_CSR(hvictl, CSR_HVICTL)
 DECLARE_CSR(henvcfg, CSR_HENVCFG)
 DECLARE_CSR(hstateen0, CSR_HSTATEEN0)
 DECLARE_CSR(hstateen1, CSR_HSTATEEN1)
@@ -4594,11 +4639,15 @@ DECLARE_CSR(hstateen3, CSR_HSTATEEN3)
 DECLARE_CSR(htval, CSR_HTVAL)
 DECLARE_CSR(hip, CSR_HIP)
 DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(hviprio1, CSR_HVIPRIO1)
+DECLARE_CSR(hviprio2, CSR_HVIPRIO2)
 DECLARE_CSR(htinst, CSR_HTINST)
 DECLARE_CSR(hgatp, CSR_HGATP)
 DECLARE_CSR(hcontext, CSR_HCONTEXT)
 DECLARE_CSR(hgeip, CSR_HGEIP)
+DECLARE_CSR(vstopi, CSR_VSTOPI)
 DECLARE_CSR(scountovf, CSR_SCOUNTOVF)
+DECLARE_CSR(stopi, CSR_STOPI)
 DECLARE_CSR(utvt, CSR_UTVT)
 DECLARE_CSR(unxti, CSR_UNXTI)
 DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
@@ -4621,6 +4670,8 @@ DECLARE_CSR(mideleg, CSR_MIDELEG)
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mvien, CSR_MVIEN)
+DECLARE_CSR(mvip, CSR_MVIP)
 DECLARE_CSR(menvcfg, CSR_MENVCFG)
 DECLARE_CSR(mstateen0, CSR_MSTATEEN0)
 DECLARE_CSR(mstateen1, CSR_MSTATEEN1)
@@ -4634,6 +4685,9 @@ DECLARE_CSR(mtval, CSR_MTVAL)
 DECLARE_CSR(mip, CSR_MIP)
 DECLARE_CSR(mtinst, CSR_MTINST)
 DECLARE_CSR(mtval2, CSR_MTVAL2)
+DECLARE_CSR(miselect, CSR_MISELECT)
+DECLARE_CSR(mireg, CSR_MIREG)
+DECLARE_CSR(mtopei, CSR_MTOPEI)
 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
@@ -4792,10 +4846,20 @@ DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
 DECLARE_CSR(mhartid, CSR_MHARTID)
 DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR)
+DECLARE_CSR(mtopi, CSR_MTOPI)
+DECLARE_CSR(sieh, CSR_SIEH)
+DECLARE_CSR(siph, CSR_SIPH)
 DECLARE_CSR(stimecmph, CSR_STIMECMPH)
+DECLARE_CSR(vsieh, CSR_VSIEH)
+DECLARE_CSR(vsiph, CSR_VSIPH)
 DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH)
 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
+DECLARE_CSR(hidelegh, CSR_HIDELEGH)
+DECLARE_CSR(hvienh, CSR_HVIENH)
 DECLARE_CSR(henvcfgh, CSR_HENVCFGH)
+DECLARE_CSR(hviph, CSR_HVIPH)
+DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H)
+DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H)
 DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H)
 DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H)
 DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H)
@@ -4833,11 +4897,16 @@ DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
 DECLARE_CSR(mstatush, CSR_MSTATUSH)
+DECLARE_CSR(midelegh, CSR_MIDELEGH)
+DECLARE_CSR(mieh, CSR_MIEH)
+DECLARE_CSR(mvienh, CSR_MVIENH)
+DECLARE_CSR(mviph, CSR_MVIPH)
 DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H)
 DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H)
 DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H)
 DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H)
+DECLARE_CSR(miph, CSR_MIPH)
 DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H)
 DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H)
 DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H)
diff --git a/src/target/riscv/gdb_regs.h b/src/target/riscv/gdb_regs.h
index 3a46577..08926b5 100644
--- a/src/target/riscv/gdb_regs.h
+++ b/src/target/riscv/gdb_regs.h
@@ -98,6 +98,8 @@ enum gdb_regno {
 	GDB_REGNO_MEPC = CSR_MEPC + GDB_REGNO_CSR0,
 	GDB_REGNO_MCAUSE = CSR_MCAUSE + GDB_REGNO_CSR0,
 	GDB_REGNO_SATP = CSR_SATP + GDB_REGNO_CSR0,
+	GDB_REGNO_MTOPI = CSR_MTOPI + GDB_REGNO_CSR0,
+	GDB_REGNO_MTOPEI = CSR_MTOPEI + GDB_REGNO_CSR0,
 	GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
 	GDB_REGNO_PRIV = 4161,
 	/* It's still undecided what register numbers GDB will actually use for
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 3043b06..e15384a 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1725,16 +1725,30 @@ static int examine(struct target *target)
 		return ERROR_FAIL;
 	}
 
-	uint64_t vlenb;
-	if (register_read_direct(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) {
+	uint64_t value;
+	if (register_read_direct(target, &value, GDB_REGNO_VLENB) != ERROR_OK) {
 		if (riscv_supports_extension(target, 'V'))
 			LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work.");
 		r->vlenb = 0;
 	} else {
-		r->vlenb = vlenb;
+		r->vlenb = value;
 		LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb);
 	}
 
+	if (register_read_direct(target, &value, GDB_REGNO_MTOPI) == ERROR_OK) {
+		r->mtopi_readable = true;
+
+		if (register_read_direct(target, &value, GDB_REGNO_MTOPEI) == ERROR_OK) {
+			LOG_TARGET_INFO(target, "S?aia detected with IMSIC");
+			r->mtopei_readable = true;
+		} else {
+			r->mtopei_readable = false;
+			LOG_TARGET_INFO(target, "S?aia detected without IMSIC");
+		}
+	} else {
+		r->mtopi_readable = false;
+	}
+
 	/* Now init registers based on what we discovered. */
 	if (riscv_init_registers(target) != ERROR_OK)
 		return ERROR_FAIL;
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index f5f2332..3c91526 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5460,6 +5460,72 @@ int riscv_init_registers(struct target *target)
 				case CSR_MCOUNTEREN:
 					r->exist = riscv_supports_extension(target, 'U');
 					break;
+
+				/* Interrupts M-Mode CSRs. */
+				case CSR_MISELECT:
+				case CSR_MIREG:
+				case CSR_MTOPI:
+				case CSR_MVIEN:
+				case CSR_MVIP:
+					r->exist = info->mtopi_readable;
+					break;
+				case CSR_MTOPEI:
+					r->exist = info->mtopei_readable;
+					break;
+				case CSR_MIDELEGH:
+				case CSR_MVIENH:
+				case CSR_MVIPH:
+					r->exist = info->mtopi_readable &&
+						riscv_xlen(target) == 32 &&
+						riscv_supports_extension(target, 'S');
+					break;
+				case CSR_MIEH:
+				case CSR_MIPH:
+					r->exist = info->mtopi_readable;
+					break;
+				/* Interrupts S-Mode CSRs. */
+				case CSR_SISELECT:
+				case CSR_SIREG:
+				case CSR_STOPI:
+					r->exist = info->mtopi_readable &&
+						riscv_supports_extension(target, 'S');
+					break;
+				case CSR_STOPEI:
+					r->exist = info->mtopei_readable &&
+						riscv_supports_extension(target, 'S');
+					break;
+				case CSR_SIEH:
+				case CSR_SIPH:
+					r->exist = info->mtopi_readable &&
+						riscv_xlen(target) == 32 &&
+						riscv_supports_extension(target, 'S');
+					break;
+				/* Interrupts Hypervisor and VS CSRs. */
+				case CSR_HVIEN:
+				case CSR_HVICTL:
+				case CSR_HVIPRIO1:
+				case CSR_HVIPRIO2:
+				case CSR_VSISELECT:
+				case CSR_VSIREG:
+				case CSR_VSTOPI:
+					r->exist = info->mtopi_readable &&
+						riscv_supports_extension(target, 'V');
+					break;
+				case CSR_VSTOPEI:
+					r->exist = info->mtopei_readable &&
+						riscv_supports_extension(target, 'V');
+					break;
+				case CSR_HIDELEGH:
+				case CSR_HVIENH:
+				case CSR_HVIPH:
+				case CSR_HVIPRIO1H:
+				case CSR_HVIPRIO2H:
+				case CSR_VSIEH:
+				case CSR_VSIPH:
+					r->exist = info->mtopi_readable &&
+						riscv_xlen(target) == 32 &&
+						riscv_supports_extension(target, 'V');
+					break;
 			}
 
 			if (!r->exist && !list_empty(&info->expose_csr)) {
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 6b4d577..a6a1f93 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -124,6 +124,9 @@ typedef struct {
 	 * Zve* extensions implement vector registers without setting misa.V. */
 	unsigned int vlenb;
 
+	bool mtopi_readable;
+	bool mtopei_readable;
+
 	/* The number of triggers per hart. */
 	unsigned int trigger_count;