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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-19 20:43:47 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-07-02 10:15:20 +0300 |
| commit | 3883b03aaafef5e1eff423664f7ea2e1d8f14ba4 (patch) | |
| tree | 997ec7890005a72a065504c7c4f4e50f17b8524f /.github | |
| parent | cb87885c0067840962b65d7ebb86de6949cb5967 (diff) | |
| download | riscv-openocd-3883b03aaafef5e1eff423664f7ea2e1d8f14ba4.zip riscv-openocd-3883b03aaafef5e1eff423664f7ea2e1d8f14ba4.tar.gz riscv-openocd-3883b03aaafef5e1eff423664f7ea2e1d8f14ba4.tar.bz2 | |
target/riscv: separate register cache stuff into files
This commit creates file structure for register cache related
functions.
Specifically:
* `riscv_reg.h` -- general interface to registers. Safe to use after
register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
`riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
registers. Will be extended as needed once other functionality (not
related to register access) is separated (e.g. DM/DTM specific stuff).
Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Diffstat (limited to '.github')
0 files changed, 0 insertions, 0 deletions