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# vector scalar instructions
stop    31..25=0 24..20=0 19..15=0 14..12=5 11..7=0 6..2=0x1D 1..0=3
utidx   31..25=0 24..20=0 19..15=0 14..12=6 rd      6..2=0x1D 1..0=3
movz    31..25=0 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
movn    31..25=1 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
fmovz   31..25=2 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
fmovn   31..25=3 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3

# rocc format, xd = inst[14], xs1 = inst[13], xs2 = inst[12]

# vector instructions
vsetcfg      imm12             rs1      14=0 13=1 12=0 11..7=0 6..2=0x02 1..0=3
vsetvl       31..25=0 24..20=0 rs1      14=1 13=1 12=0 rd      6..2=0x02 1..0=3
vsetprec     imm12             19..15=1 14=0 13=0 12=0 11..7=0 6..2=0x16 1..0=3
vgetcfg      31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3
vgetvl       31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3

vmvv         31..25=1 24..20=0 rs1      14=0 13=0 12=0 rd      6..2=0x0A 1..0=3
vmsv         31..25=1 24..20=0 rs1      14=0 13=1 12=0 rd      6..2=0x0A 1..0=3
vf           imm12hi  24..20=1 rs1      14=0 13=1 12=0 imm12lo 6..2=0x0A 1..0=3

# vector supervisor instructions
vxcptcause   31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x0A 1..0=3
vxcptaux     31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x0A 1..0=3

vxcptsave    31..25=0 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
vxcptrestore 31..25=1 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
vxcptkill    31..25=2 24..20=0 19..15=0 14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3

vxcptevac    31..25=3 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
vxcpthold    31..25=4 24..20=0 19..15=0 14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
venqcmd      31..25=5 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
venqimm1     31..25=6 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
venqimm2     31..25=7 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
venqcnt      31..25=8 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3

#                              3=d
#                              2=w
#                    1=f  1=u  1=h                   0    1    1=strided
#           3-bits   0=x  0=s  0=b                   0    1    0=unit-strided
#           ---------------------------------------------------------------------------
#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
#           |        |    |    |                     |    |    |       |
vlsegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlsegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlsegwu     vseglen  28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlsegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlseghu     vseglen  28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlsegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vlsegbu     vseglen  28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vflsegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
vflsegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3

#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
#           |        |    |    |                     |    |    |       |
vlsegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegstwu   vseglen  28=0 27=1 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegsthu   vseglen  28=0 27=1 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vlsegstbu   vseglen  28=0 27=1 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vflsegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
vflsegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3

#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
#           |        |    |    |                     |    |    |       |
vssegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
vssegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
vssegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
vssegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
vfssegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
vfssegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3

#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
#           |        |    |    |                     |    |    |       |
vssegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
vssegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
vssegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
vssegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
vfssegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
vfssegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3