riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2026-03-24	ext-p : update table to v0.20 (#413)	Chih-Min Chao	1	-0/+2
	Quoted from spec "This version (020) differs from the previous one (019) with the addition of: * SHL instructions (shift left or right, logical) that are unsigned versions of the SHA instructions (shift left or right, arithmetic); and * for RV64 only, ‘P’-suffi x versions of PNCLIP instructions that are similar to RV32 PNCLIP instructions without shifting or rounding. The complete set of instructions added for RV32 are: PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS And for RV64: PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W" reference: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2026-03-13	fix absolute path for inst.go codegen (#411)	Meng Zhuo	2	-4/+4
	sys.args will print out absolute path like "/x/y/z/src/riscv_opcodes/__main__.py -go ..." the path will changed if generated on another path. This PR replace the absolute path with "make inst.go " for stable code generation.
2026-03-11	Refine rvp (#409)	Chih-Min Chao	1	-0/+63
	* rvp: Add P extension This commit add encodings for P Extension: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Signed-off-by: 2011eric <201165r1c@gmail.com> * rvp: rename pmqwacc/mqrwacc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: pdif has been renamed by pabd Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: fix some missing characters in instructions name Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: ppack has been renamed by ppair Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: add missing instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: remove old grevi Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: convert 56 RV32 scalar instructions to pseudo-instructions of RV64 equivalents Based on RVP-instrEncodings-019.pdf, converted RV32 scalar instructions that share the same encoding with RV64 packed-word instructions to pseudo-instructions. Instructions converted (56 total): - Pages 4-8: sslai, ssha, sshar (3) - Page 9: sadd, aadd, saddu, aaddu, ssub, asub, ssubu, asubu (8) - Page 10: mul.h01, macc.h01, mulu.h01, maccu.h01 (4) - Page 11: sh1sadd (1) - Page 12: mul/macc/mulu/maccu/mulsu/maccsu.h00/h11 (12) - Page 14: mqacc.h01, mqracc.h01 (2) - Page 15: mseq, mslt, msltu (3) - Page 16: mulhr, mhacc, mhracc, mulhru, mhaccu, mhraccu, mulh.h0/h1, mulhsu.h0/h1, mhacc.h0/h1, mhaccsu.h0/h1, mulhrsu, mhaccsu, mhraccsu, mulq, mulqr, mqacc.h00/h11, mqracc.h00/h11 (23) Also removed packbt/packtb/packt pseudo-instructions that referenced non-existent rv64_p instructions. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: align indent and add comment by page Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: fix mnemonic typo Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvp: add P-extension scalar pseudo-ops to emitted_pseudo_ops --------- Signed-off-by: 2011eric <201165r1c@gmail.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Co-authored-by: 2011eric <201165r1c@gmail.com>
2026-02-09	Generate instruction based on extension for SpinalHDL (#405)	Inochi Amaoto	1	-16/+18
	Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
2026-01-28	Fix spinalhdl MaskedLiteral (#403)	Jack Davine	1	-1/+1

2025-10-13	Reorganise Python code using pyproject.toml (#378)	Andrew Waterman	14	-0/+2113
	Add pyproject.toml (the modern alternative to requirements.txt), making this a proper Python package that can be installed via pip and potentially uploaded to PyPI. This also loads the files using `importlib.resources` and installs them into the wheel. This means that when you create a wheel using `uv build` it will still be able to load all the opcodes and CSV files. To avoid moving those resource files in the source repo, the Python build backend (hatchling) is instructed to move them to the right place when building a wheel, and the `resource_root()` function checks in both places so it always works. This is a little hacky but it works. CI builds source and binary wheels (not actually binary) that can be uploaded to PyPI. If we do upload them then using this project is as simple as ``` uvx riscv_opcodes -c 'rv*' ``` Co-authored-by: Tim Hutt <timothy.hutt@codasip.com>