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2019-08-03
(Partially) fix #30 (#31)
Tommy Thorn
1
-1084
/
+0
2019-06-18
v-spec 0.7.1-0607 (#29)
Chih-Min Chao
1
-0
/
+1
2019-06-16
More hypervisor v0.4 updates
Andrew Waterman
1
-1
/
+1
2019-06-16
Updates for hypervisor v0.4
Andrew Waterman
1
-13
/
+14
2019-05-16
rvv: add vector register field and control register
Chih-Min Chao
1
-1
/
+18
2019-05-14
zimm -> uimm in CSR instruction listing
Andrew Waterman
1
-2
/
+2
2019-04-26
Create RVQ listing in latex table
Andrew Waterman
1
-0
/
+16
2019-04-22
Add missing N-extension CSRs
Andrew Waterman
1
-0
/
+8
2019-02-28
Read opcodes from files (#23)
Pavel I. Kryukov
1
-61
/
+74
2019-02-11
Add SystemVerilog generation (#24)
Florian Zaruba
1
-0
/
+21
2019-01-22
Add tentative CSR assignment for fast-interrupt group's CLIC proposal
Andrew Waterman
1
-0
/
+17
2019-01-21
Add tentative hypervisor CSR and instruction encodings
Andrew Waterman
1
-1
/
+19
2018-11-20
Don't label latex tables
Andrew Waterman
1
-1
/
+0
2018-11-20
Exclude ECALL/EBREAK from privileged instruction table
Andrew Waterman
1
-3
/
+1
2018-11-19
Modernize to Python 3 (#22)
Pavel I. Kryukov
1
-111
/
+114
2018-11-06
Separate FENCE.I and CSRRx from RV32I table
Andrew Waterman
1
-9
/
+15
2018-09-20
Add header following Go convention for generated code (#21)
Tobias Klauser
1
-1
/
+1
2018-08-25
Improve TeX output for FENCE instructions
Andrew Waterman
1
-1
/
+1
2018-08-06
FENCE has a field called FM in bits 31:28
Andrew Waterman
1
-1
/
+2
2018-07-17
Make the hashbang portable (#20)
Edward Tomasz NapieraĆa
1
-1
/
+1
2017-11-27
Rename sptbr to satp and sbadaddr to stval
Andrew Waterman
1
-3
/
+3
2017-05-17
Merge remote-tracking branch 'origin/priv-1.10'
Palmer Dabbelt
1
-15
/
+38
2017-05-07
SB->B; UJ->J
Andrew Waterman
1
-2
/
+2
2017-04-25
Add ECALL/EBREAK to privileged instruction table
Andrew Waterman
1
-0
/
+2
2017-04-25
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman
1
-2
/
+2
2017-04-25
Remove hret instruction
Andrew Waterman
1
-1
/
+1
2017-03-31
Support generating Go code (#3)
Benjamin Barenblat
1
-0
/
+41
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-3
/
+6
2017-03-23
Add PMP
Andrew Waterman
1
-0
/
+20
2017-03-09
New counter-enable mechanism
Andrew Waterman
1
-2
/
+2
2017-02-20
Remove sfence.vm and add sfence.vma
Andrew Waterman
1
-5
/
+3
2016-12-21
Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space
Kito Cheng
1
-1
/
+1
2016-08-26
Renumber misa; add performance counter CSRs
Andrew Waterman
1
-33
/
+154
2016-08-25
Re-rename trigger registers to be 1-based
Andrew Waterman
1
-3
/
+3
2016-08-25
Make hardware triggers match latest spec.
Tim Newsome
1
-4
/
+4
2016-06-30
Remove instructions from privilege spec that are already in user spec
Andrew Waterman
1
-5
/
+2
2016-06-17
Remove sasid (it's merged into sptbr now)
Andrew Waterman
1
-1
/
+0
2016-06-08
Add breakpoint CSRs
Andrew Waterman
1
-0
/
+4
2016-06-01
Add dret instruction and debug CSRs. (#5)
Tim Newsome
1
-0
/
+3
2016-05-13
Remove arg lists from latex tables
Andrew Waterman
1
-42
/
+1
2016-05-02
Remove mipi registers
Andrew Waterman
1
-1
/
+0
2016-05-02
Remove tohost/fromhost
Andrew Waterman
1
-2
/
+0
2016-04-30
Remove mcfgaddr; change memory map
Andrew Waterman
1
-2
/
+1
2016-04-30
Remove mtimecmp
Andrew Waterman
1
-2
/
+0
2016-04-30
ERET -> xRET
Andrew Waterman
1
-1
/
+1
2016-04-06
Remove nonstandard stats, uarch CSRs
Andrew Waterman
1
-21
/
+0
2016-03-03
Update CSR encoding
Andrew Waterman
1
-0
/
+19
2016-02-28
WIP on priv spec v1.9
Andrew Waterman
1
-30
/
+14
2016-02-28
WIP on priv spec v1.9
Andrew Waterman
1
-16
/
+15
2016-02-05
WIP on priv spec v1.9
Andrew Waterman
1
-5
/
+4
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