index
:
riscv-tools/riscv-opcodes.git
confprec
debug
incoresemi-migration-to-new-format
llvm-encodings
master
mvp
riscv-bitmanip
rnmi
rvv
v
vadc
wfmi
zfh
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
opcodes
Age
Commit message (
Collapse
)
Author
Files
Lines
2015-05-09
Update to privileged architecture version 1.7
Andrew Waterman
1
-0
/
+3
2015-03-17
Merge [shm]call into ecall, [shm]ret into eret
Andrew Waterman
1
-6
/
+3
2015-03-12
Add hcall instruction
Andrew Waterman
1
-0
/
+1
2015-03-12
Update to new privileged spec
Andrew Waterman
1
-9
/
+13
2014-03-11
New FP encoding
Andrew Waterman
1
-69
/
+65
2014-03-06
Add fclass.{s|d} instructions
Andrew Waterman
1
-4
/
+6
2014-01-13
swap JAL/JALR again
Andrew Waterman
1
-5
/
+5
2013-11-25
New privileged ISA
Andrew Waterman
1
-36
/
+35
2013-11-21
fix slli/slliw encoding bug
Yunsup Lee
1
-2
/
+2
2013-09-21
Update ISA encoding
Andrew Waterman
1
-186
/
+181
2013-08-06
Rename MTFSR/MFFSR to FSSR/FRSR
Andrew Waterman
1
-2
/
+2
2013-07-31
HW ignores upper bits of fence, but SW supplies 0
Andrew Waterman
1
-4
/
+4
2013-07-31
Swap J and JALR encodings
Andrew Waterman
1
-2
/
+2
2013-07-26
change supervisor encoding
Yunsup Lee
1
-5
/
+5
2013-07-26
Factor out Hwacha/RVC and rename MFTX/MXTF to FMV
Andrew Waterman
1
-190
/
+4
2013-07-25
Refactor parse-opcodes
Andrew Waterman
1
-25
/
+27
2013-07-25
Remove JALR static hints
Andrew Waterman
1
-3
/
+1
2013-07-23
Remove CFLUSH
Andrew Waterman
1
-1
/
+0
2013-04-17
add auipc, lr, sc
Andrew Waterman
1
-1
/
+6
2012-03-24
new supervisor mode
Andrew Waterman
1
-18
/
+17
2012-03-18
change vector fence names/encoding
Andrew Waterman
1
-8
/
+4
2012-03-18
clean up vector exception instructions
Yunsup Lee
1
-7
/
+10
2012-03-13
add more instructions for vector exception handling
Yunsup Lee
1
-1
/
+5
2012-03-13
add vvcfg,vtcfg
Yunsup Lee
1
-0
/
+2
2012-03-13
opcodes cleanup
Yunsup Lee
1
-7
/
+6
2012-03-10
slight change to vector supervisor instructions
Yunsup Lee
1
-4
/
+4
2012-03-03
new instructions to handle vector exceptions
Yunsup Lee
1
-0
/
+6
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+380
2011-06-19
Renamed packages
Andrew Waterman
1
-380
/
+0
2011-05-15
[opcodes,pk,sim,xcc] resolve a conflict
Yunsup Lee
1
-6
/
+6
2011-05-15
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Yunsup Lee
1
-89
/
+107
2011-05-13
tweaked encoding of rdcycle & cousins
Andrew Waterman
1
-5
/
+8
2011-05-06
[opcodes] reordered RVC instructions
Andrew Waterman
1
-13
/
+14
2011-04-24
[xcc,sim,opcodes] added c.addiw
Andrew Waterman
1
-0
/
+2
2011-04-24
[xcc,sim,opcodes] added more RVC instructions
Andrew Waterman
1
-4
/
+26
2011-04-18
[xcc,sim,opcodes] added rvc conditional branches
Andrew Waterman
1
-12
/
+14
2011-04-12
[xcc,pk,sim] added privileged cflush instruction
Andrew Waterman
1
-0
/
+1
2011-04-12
[xcc,sim] rvc loads and stores
Andrew Waterman
1
-4
/
+12
2011-04-11
[xcc,sim,opcodes] more rvc instructions and bug fixes
Andrew Waterman
1
-2
/
+4
2011-04-09
[xcc, sim] added rvc insn c.li; misc fixes
Andrew Waterman
1
-1
/
+2
2011-04-09
[xcc,pk,sim,opcodes] added first RVC instruction
Andrew Waterman
1
-5
/
+6
2011-04-06
[opcodes,pk,sim,xcc] fix utidx - add rd
Yunsup Lee
1
-1
/
+1
2011-04-05
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵
Yunsup Lee
1
-43
/
+113
instructions
2011-04-04
[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
Yunsup Lee
1
-0
/
+6
2011-04-04
[opcodes,pk,sim,xcc] add vector mem instructions
Yunsup Lee
1
-0
/
+38
2011-04-04
[opcodes,pk,sim,xcc] add stop,utidx instructions
Yunsup Lee
1
-0
/
+2
2011-04-04
[opcodes,pk,sim,xcc] add fence instructions for vector unit
Yunsup Lee
1
-2
/
+6
2011-03-25
[opcodes] minor opcode changes
Andrew Waterman
1
-17
/
+17
2011-03-25
[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
Andrew Waterman
1
-4
/
+0
2011-03-25
[xcc,pk,opcodes,sim] updated encoding/insn names
Andrew Waterman
1
-34
/
+46
[next]