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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2012-03-13 10:14:08 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2012-03-13 10:14:08 -0700 |
commit | 20e4f0285c563e5a403bd6ba735beadbbd3c203e (patch) | |
tree | 4605339bf9b30e205faba4fe4c02b91e1c891c70 /opcodes | |
parent | ac54233d70740becc0e9031f13fee12060809a5e (diff) | |
download | riscv-opcodes-20e4f0285c563e5a403bd6ba735beadbbd3c203e.zip riscv-opcodes-20e4f0285c563e5a403bd6ba735beadbbd3c203e.tar.gz riscv-opcodes-20e4f0285c563e5a403bd6ba735beadbbd3c203e.tar.bz2 |
opcodes cleanup
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes | 13 |
1 files changed, 6 insertions, 7 deletions
@@ -138,7 +138,6 @@ venqimm1 31..27=0 rs1 rs2 16..7=0x201 6..2=0x1E 1..0=3 venqimm2 31..27=0 rs1 rs2 16..7=0x202 6..2=0x1E 1..0=3 venqcnt 31..27=0 rs1 rs2 16..7=0x203 6..2=0x1E 1..0=3 vwaitxcpt 31..27=0 26..22=0 21..17=0 16..7=0x300 6..2=0x1E 1..0=3 -vwaitkill 31..27=0 26..22=0 21..17=0 16..7=0x301 6..2=0x1E 1..0=3 # 0x7C-0x7F are reserved for >32b instructions @@ -197,12 +196,12 @@ fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3 fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3 fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3 -mftx.s rd 26..22=0 rs2 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3 -mftx.d rd 26..22=0 rs2 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3 -mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3 -mxtf.s rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3 -mxtf.d rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3 -mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3 +mftx.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3 +mftx.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3 +mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3 +mxtf.s rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3 +mxtf.d rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3 +mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3 flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3 fld rd rs1 imm12 9..7=3 6..2=0x01 1..0=3 |