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2021-03-11update vmv.x.s opcode (#65)leahyao1-1/+1
2021-02-23rvv: add vsetivliChih-Min Chao1-3/+4
2021-02-23rvv: rename reciprocal instructionsChih-Min Chao1-2/+2
2021-02-23rvv: add vle1/vse1 instructionsChih-Min Chao1-0/+2
2020-12-02rvv: follow change of indexed ordered/unordered load/storeChih-Min Chao1-26/+36
2020-12-02rvv: remove quad instructionsChih-Min Chao1-5/+0
2020-09-17Add encodings of vfrsqrte7.v and vfrece7.v (#49)Zhen Wei1-0/+2
2020-08-03Make *.vv operand naming be consistent with type (#46)Zhen Wei1-48/+48
2020-07-27rvv: add eew 128 ~ 1024 load/store opcodeChih-Min Chao1-33/+65
2020-07-27rvv: add whole ldst pseudo instruction and update reference linkChih-Min Chao1-1/+1
2020-07-21Add vrgatherei16.vvAndrew Waterman1-10/+11
2020-07-21Incorporate whole-register load/store changes in RVV v1.0-draftAndrew Waterman1-2/+20
2020-05-12RVV v0.9: AMOs with explicit element widthsAndrew Waterman1-19/+39
2020-05-12RVV v0.9: loads/stores with explicit element widthsAndrew Waterman1-45/+33
2020-05-12RVV v0.9: change vl1r/vs1r opcodesAndrew Waterman1-2/+2
2020-05-12RVV v0.9: new extension instructionsAndrew Waterman1-0/+9
2020-05-12RVV v0.9: move VFUNARY0/VFUNARY1 opcodesAndrew Waterman1-26/+26
2020-03-28Add FP->int truncating conversionsAndrew Waterman1-17/+23
2020-03-28Add vfslide1up/downAndrew Waterman1-8/+10
2019-11-28Remove vamo*q; replace vamo*d with vamo*eAndrew Waterman1-19/+9
2019-11-28Add vmv<nf>r.vAndrew Waterman1-0/+4
2019-11-28rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wiChih-Min Chao1-12/+12
2019-11-28rvv: add load/store whole registerChih-Min Chao1-2/+7
2019-11-28rvv: replace vfncvt suffix with .wChih-Min Chao1-6/+6
2019-11-28rvv: add vqmacc variant insnChih-Min Chao1-0/+9
2019-11-15Remove scaled fixed-point multiply-add instructionsAndrew Waterman1-8/+0
2019-11-15vcompress is encoded with vm=1Andrew Waterman1-1/+1
2019-11-15Add vaaddu/vasubu; change vaadd/vasub opcodesAndrew Waterman1-5/+10
2019-11-11Update encoding of vadc and friendsAndrew Waterman1-10/+10
2019-11-11Add vfncvt.rod.f.f.v instructionAndrew Waterman1-5/+6
2019-09-17vwmaccsu/us opcodes have been swappedAndrew Waterman1-6/+6
2019-08-26More updates to rvv encodingAndrew Waterman1-13/+11
2019-07-15vext.x.v -> vmv.x.sAndrew Waterman1-1/+1
2019-07-05Fix encoding of vfclass.v instructionAndrew Waterman1-1/+1
2019-06-28vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcodeAndrew Waterman1-2/+2
2019-06-18v-spec 0.7.1-0607 (#29)Chih-Min Chao1-41/+73
2019-06-11Expand vfunary0 and vfunary1 opcodes into sub-instructionsAndrew Waterman1-2/+20
2019-06-05More V 0.7.1 updatesAndrew Waterman1-12/+10
2019-06-05Some V 0.7.1 updatesAndrew Waterman1-9/+18
2019-06-05VMV.S.X requires vs2=0Andrew Waterman1-2/+2
2019-05-17Expand vmunary0 into its constituent instructionsAndrew Waterman1-1/+6
2019-05-17vmv/vext/vfmv are reserved when vm=0Andrew Waterman1-4/+4
2019-05-17vadc/vsbc require vm=1Andrew Waterman1-5/+5
2019-05-16rvv: vector instruction encodingChih-Min Chao1-0/+378
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