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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-05-29 06:11:10 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-28 15:11:10 -0700 |
| commit | 5181d13bef845edfb511e3132a7e661090e3204b (patch) | |
| tree | 42e44b93ffee3fef5ad1b89e299040747c2d8999 | |
| parent | 37eee46346f244050ef1e5a034cf930ee34a7acc (diff) | |
| download | riscv-opcodes-5181d13bef845edfb511e3132a7e661090e3204b.zip riscv-opcodes-5181d13bef845edfb511e3132a7e661090e3204b.tar.gz riscv-opcodes-5181d13bef845edfb511e3132a7e661090e3204b.tar.bz2 | |
Update rv_v to fix typo (#251)
Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
| -rw-r--r-- | rv_v | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -62,7 +62,7 @@ vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -# Unit-stride F31..29=0ault-Only-First Loads +# Unit-stride Fault-Only-First Loads # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 |