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2023-05-13add amocas.w/d zacas instructionsVed Shanbhogue1-0/+2
2023-05-02Merge pull request #167 from Lucas-Wye/masterNeel Gala1-2/+28
change decode generation part of chisel
2023-05-02Merge pull request #154 from rivosinc/zvk-vector-cryptoNeel Gala14-8/+218
Support for Zvk, Vector Cryptography Extensions
2023-05-01Support for Zvk, Vector Cryptography ExtensionsEric Gouriou14-8/+218
Add encodings for all instructions in the Zvk extensions: - Zvbb, Vector Bit-manipulation instructions used in Cryptography, - Zvbc, Vector Carryless Multiplication - Zvkg, Vector GCM/GMAC instruction for Cryptography, - Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single Round), - Zvknha, Zvknhb, NIST Suite: Vector SHA-2, - Zvksed, ShangMi Suite: SM4 Block Cipher Instructions - Zvkssh, ShangMi Suite: SM3 Hash Function Instructions Add two "shorthand" extensions: - Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh - Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh Three new fields are listed in constants.py: - 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh), and 5-bit shift constant (vwsll.vi in Zvbb) - 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount in vror.vi. The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the P opcode space. Some encodings conflict with proposed instructions in the P extension (packed SIMD). Zvk and P are exclusive of each other, no implementation will implement both. Conflicting P instructions are marked as pseudo of the Zvk instructions. The encodings match the current documentation of the specification at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>, at Version v0.9.1, 25 April, 2023 (Freeze Candidate). Co-authored-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-04-19Merge pull request #174 from liweiwei90/plct-bf16-devAndrew Waterman3-0/+6
Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.
2023-04-15Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.Weiwei Li3-0/+6
2023-04-07Merge pull request #172 from dramforever/instr_dict_extension_fixNeel Gala1-6/+8
Fix merging of instructions with the same name
2023-04-07Fix merging of instructions with the same namedramforever1-6/+8
Fixes generation of 'extension' field for instr_dict.yaml
2023-03-17use val instead of defLucas-Wye1-5/+1
2023-03-16Merge pull request #170 from ptomsich/ptomsich/zfaPhilipp Tomsich6-0/+33
Add (unratified) Zfa extension
2023-03-17Add (unratified) Zfa extensionPhilipp Tomsich6-0/+33
Zfa adds 'missing' floating-point functionality: - fli.[hsdq]: floating-point load-immediate - fminm/fmaxm.[hsdq]: IEEE 754-2019 minimum and maximum - fround(nx)?.[hsdq]: IEEE 754-2019 roundToIntegral(Exact)? - fcvtmod.w.d: ECMAScript modular float->integer conversion - move instructions for XLEN < FLEN - comparisons that support quiet NaN inputs This adds a surprisingly large number of files, as the instructions added with Zfa depend on context (e.g., .h-variants become available only if Zfh is present).
2023-03-16Merge pull request #169 from riscv/smrnmiAndrew Waterman1-0/+1
Add Smrnmi MNRET instruction
2023-03-16Add Smrnmi MNRET instructionAndrew Waterman1-0/+1
Forgot to add this as part of #168.
2023-03-16Merge pull request #168 from riscv/smrnmiAndrew Waterman2-0/+8
Add Snrmni CSR and field definitions
2023-03-16Add Snrmni CSR and field definitionsAndrew Waterman2-0/+8
2023-03-10change the generation part of chiselLucas-Wye1-2/+32
2023-02-27Merge pull request #166 from eflaner/masterNeel Gala3-3/+0
Removing "grev & grevi" instructions from "unratified/rv*_zbpbo" sub-extensions
2023-02-27Removing all "grev" instances from "zbpbo" sub-extensionsBabu P S3-3/+0
GREV instruction no longer exist in the zbpbo specified by [v0.9.11 spec](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#51-zbpbo)
2023-02-14Move Zawrs to ratified folder (#162)ved-rivos1-0/+0
* Move Zawrs to ratified folder * Move Zawrs to ratified folder
2023-02-06Merge pull request #159 from riscv/revert-158Neel Gala10-329/+322
Revert #158, restoring #147
2023-02-06Revert "Revert "Fix pack instruction in rv_zbpbo""Andrew Waterman1-1/+1
This reverts commit 24cba79065aa975ad91e92c5d59f2e1dafa5ab26.
2023-02-06Revert "Revert "Removing import of csrrs and crrci in rv_zpn""Andrew Waterman1-2/+0
This reverts commit 3485bbcda5509615e4d18708722d67871efb7eaf.
2023-02-06Revert "Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)""Andrew Waterman10-330/+325
This reverts commit 6b5a0648ab6b99507aef3c902afbcd3cd9d90353.
2023-02-05Merge pull request #158 from riscv/revert-p-temporarilyAndrew Waterman10-322/+329
Temporarily revert #147
2023-02-05Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)"Andrew Waterman10-325/+330
This reverts commit 9b0eddd52b9e3c1fbd1dab56ecbaa88747254a2a.
2023-02-05Revert "Removing import of csrrs and crrci in rv_zpn"Andrew Waterman1-0/+2
This reverts commit 2cf6da8f9a370ee5c0012d4ae4f403c3d920d1e8.
2023-02-05Revert "Fix pack instruction in rv_zbpbo"Andrew Waterman1-1/+1
This reverts commit 115e4237407e8c02b945dfb12c086ee57200dd55.
2023-01-31Merge pull request #157 from riscv/work-around-147Andrew Waterman0-0/+0
Temporarily work around #147 breaking Spike
2023-01-31Merge branch 'master' into work-around-147Andrew Waterman12-332/+325
2023-01-31Update encoding.h.out's copyright year.Aaron Durbin1-1/+1
It's a new year. Make the copyright clause reflect 2023.
2023-01-31Add support for SvaduAaron Durbin1-0/+4
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the A/D bits in the PTE. Provide the bit encodings for the HADE support.
2023-01-31updated readmeNeel Gala1-0/+9
2023-01-31rv32_i shift pseudo ops should depend on rv64_i (not rv128_i)Neel Gala1-0/+3
2023-01-31adding pseudo_ops for shift-ops where the mnemonics remain the sameNeel Gala2-3/+6
2023-01-31indenting logs for better readabilityNeel Gala1-2/+2
2023-01-31fix regex fpr pseudo op lookup to ensure that we don't hit on substringsNeel Gala1-1/+1
2023-01-31Add AIA registers (#143)i2h21-1/+35
2023-01-31Emit SLLI_RV128 etc. (and SLLI_RV32 etc. while we're at it)Andrew Waterman1-1/+4
2023-01-31Fix backwards incompatibility introduced by RV128 opcodes in #112Andrew Waterman3-10/+9
Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI, and SRAI. Thus, downstream tooling that relies on these to connote the RV64 variants of these instructions is semantically affected. Fix by reverting SLLI etc. to being the RV64 variants.
2023-01-31Rename RV128 shamt to shamtqAndrew Waterman2-4/+5
This will reduce the chance that people pick the wrong shamt width.
2023-01-31Add (unratified) ZiCond extension (#152)Philipp Tomsich1-0/+3
2023-01-30Merge pull request #156 from adurbin-rivos/svaduAndrew Waterman2-1/+5
svadu
2023-01-26Update encoding.h.out's copyright year.Aaron Durbin1-1/+1
It's a new year. Make the copyright clause reflect 2023.
2023-01-26Add support for SvaduAaron Durbin1-0/+4
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the A/D bits in the PTE. Provide the bit encodings for the HADE support.
2023-01-14Merge pull request #155 from riscv/fix-issues-from-153Andrew Waterman4-6/+21
Fix issues from #153
2023-01-14updated readmeNeel Gala1-0/+9
2023-01-14rv32_i shift pseudo ops should depend on rv64_i (not rv128_i)Neel Gala1-0/+3
2023-01-14adding pseudo_ops for shift-ops where the mnemonics remain the sameNeel Gala2-3/+6
2023-01-14indenting logs for better readabilityNeel Gala1-2/+2
2023-01-14fix regex fpr pseudo op lookup to ensure that we don't hit on substringsNeel Gala1-1/+1
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