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| author | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-26 13:15:00 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-31 09:28:19 -0800 |
| commit | d4c61c70b7419d0f00d14091f1c8558a03a681df (patch) | |
| tree | bbab8de51d1a8c6326e2213f5c0a269b4efa4c88 | |
| parent | 5245976d913f1e9d73836043a632ad2791037055 (diff) | |
| download | riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.zip riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.tar.gz riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.tar.bz2 | |
Add support for Svadu
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the
HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the
A/D bits in the PTE. Provide the bit encodings for the HADE support.
| -rw-r--r-- | encoding.h | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -147,9 +147,11 @@ #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 +#define MENVCFG_HADE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 +#define MENVCFGH_HADE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 #define MENVCFGH_STCE 0x80000000 @@ -182,9 +184,11 @@ #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 +#define HENVCFG_HADE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 #define HENVCFG_STCE 0x8000000000000000 +#define HENVCFGH_HADE 0x20000000 #define HENVCFGH_PBMTE 0x40000000 #define HENVCFGH_STCE 0x80000000 |