Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2019-11-04 | Update encoding of vadc and friendsvadc | Andrew Waterman | 1 | -10/+10 | |
See https://github.com/riscv/riscv-v-spec/pull/317 | |||||
2019-09-17 | vwmaccsu/us opcodes have been swapped | Andrew Waterman | 1 | -6/+6 | |
https://github.com/riscv/riscv-v-spec/pull/295 | |||||
2019-09-12 | fesvr no longer needs encoding.h | Andrew Waterman | 1 | -3/+2 | |
2019-09-12 | Add PAUSE hint instruction | Andrew Waterman | 1 | -0/+1 | |
2019-08-26 | More updates to rvv encoding | Andrew Waterman | 1 | -13/+11 | |
Closes #33 | |||||
2019-08-03 | Fix crash introduced by #30 | Andrew Waterman | 1 | -1/+1 | |
2019-08-03 | (Partially) fix #30 (#31) | Tommy Thorn | 3 | -42/+47 | |
* (Partially) fix #30 With this change (and a renamed parse-opcodes) it's possible to as a Python module without having to patch the repo. Example: from parse_opcodes import parse_inputs if __name__ == "__main__": (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"]) * Fix #30: Rename parse-opcode to parse_opcode to enable module use | |||||
2019-07-15 | vext.x.v -> vmv.x.s | Andrew Waterman | 1 | -1/+1 | |
See https://github.com/riscv/riscv-v-spec/pull/247 | |||||
2019-07-05 | Fix encoding of vfclass.v instruction | Andrew Waterman | 1 | -1/+1 | |
2019-06-28 | vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcode | Andrew Waterman | 1 | -2/+2 | |
See https://github.com/riscv/riscv-v-spec/pull/227 | |||||
2019-06-19 | Remove redundant entry from Makefile | Andrew Waterman | 1 | -1/+1 | |
2019-06-18 | v-spec 0.7.1-0607 (#29) | Chih-Min Chao | 2 | -41/+74 | |
* rvv: fault-first also support segement based on 7.8.1, add missing segment supoort for fault first load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: comparision instructions has 'm' prefix add 'm' prefix since the destination is mask register ref: https://github.com/riscv/riscv-v-spec/pull/181 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: reserved vid.v operand follow v0.7.1 change ref: https://github.com/riscv/riscv-v-spec/issues/160 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add vfrsub.vf follow v-spec 0.7.1 ref: https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add amo encoding table Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-18 | Add pseudos for RV32 shifts with correct immediate constraint | Andrew Waterman | 2 | -1/+6 | |
2019-06-16 | More hypervisor v0.4 updates | Andrew Waterman | 2 | -3/+3 | |
2019-06-16 | Updates for hypervisor v0.4 | Andrew Waterman | 1 | -13/+14 | |
2019-06-11 | Expand vfunary0 and vfunary1 opcodes into sub-instructions | Andrew Waterman | 1 | -2/+20 | |
2019-06-05 | More V 0.7.1 updates | Andrew Waterman | 1 | -12/+10 | |
2019-06-05 | Some V 0.7.1 updates | Andrew Waterman | 2 | -19/+18 | |
2019-06-05 | VMV.S.X requires vs2=0 | Andrew Waterman | 1 | -2/+2 | |
2019-05-17 | Merge branch 'chihminchao-rvv-spec-0.7' | Andrew Waterman | 4 | -4/+414 | |
2019-05-17 | Expand vmunary0 into its constituent instructions | Andrew Waterman | 1 | -1/+6 | |
Note that vmiota is being renamed to viota: https://github.com/riscv/riscv-v-spec/pull/180 | |||||
2019-05-17 | vmv/vext/vfmv are reserved when vm=0 | Andrew Waterman | 1 | -4/+4 | |
This is not currently stated in the spec, but there is a pull request to make this explicit: https://github.com/riscv/riscv-v-spec/pull/179 | |||||
2019-05-17 | vadc/vsbc require vm=1 | Andrew Waterman | 1 | -5/+5 | |
2019-05-17 | Add pseudos for masked/unmasked vmerge to help with decoding | Andrew Waterman | 2 | -2/+12 | |
2019-05-16 | rvv: vector instruction encoding | Chih-Min Chao | 2 | -2/+380 | |
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-16 | rvv: add vector register field and control register | Chih-Min Chao | 1 | -1/+18 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-14 | zimm -> uimm in CSR instruction listing | Andrew Waterman | 1 | -2/+2 | |
2019-04-26 | Create RVQ listing in latex table | Andrew Waterman | 1 | -0/+16 | |
2019-04-24 | Add RV128 opcodes (#26) | Rustem Yunusov | 2 | -4/+10 | |
2019-04-23 | Updated path to FESVR_H in Makefile (#25) | Torbjørn | 1 | -1/+1 | |
2019-04-22 | Add missing N-extension CSRs | Andrew Waterman | 1 | -0/+8 | |
2019-02-28 | Read opcodes from files (#23) | Pavel I. Kryukov | 1 | -61/+74 | |
Current generation flow assumes that opcodes are provided in a `cat ./opcodes | ./parse_opcodes -c' manner. However, Windows CMD has no `cat' command, and it uses `type' instead, so implementation of cross-platform script is complicated. In this patch, we allow parsing opcode files directly by Python, if their names are provided as a command line arguments, not depending on the host shell. If no arguments are passed, script behaves as usual, reading opcodes from the stdin. | |||||
2019-02-11 | Add SystemVerilog generation (#24) | Florian Zaruba | 2 | -0/+24 | |
2019-01-22 | Add tentative CSR assignment for fast-interrupt group's CLIC proposal | Andrew Waterman | 1 | -0/+17 | |
2019-01-21 | Add tentative hypervisor CSR and instruction encodings | Andrew Waterman | 2 | -1/+23 | |
2018-11-20 | Don't label latex tables | Andrew Waterman | 1 | -1/+0 | |
2018-11-20 | Exclude ECALL/EBREAK from privileged instruction table | Andrew Waterman | 1 | -3/+1 | |
2018-11-19 | Modernize to Python 3 (#22) | Pavel I. Kryukov | 1 | -111/+114 | |
2018-11-06 | Separate FENCE.I and CSRRx from RV32I table | Andrew Waterman | 1 | -9/+15 | |
2018-09-20 | Add header following Go convention for generated code (#21) | Tobias Klauser | 1 | -1/+1 | |
Go has a convention for generated code comments (https://golang.org/s/generatedcode), i.e. they must match the regex ^// Code generated .* DO NOT EDIT\.$ Adjust the generated header to follow this convention. | |||||
2018-09-10 | Include RVC pseudos in chisel decoder | Andrew Waterman | 1 | -1/+1 | |
2018-08-25 | Improve TeX output for FENCE instructions | Andrew Waterman | 2 | -3/+3 | |
2018-08-06 | FENCE has a field called FM in bits 31:28 | Andrew Waterman | 2 | -2/+3 | |
2018-07-17 | Make the hashbang portable (#20) | Edward Tomasz Napierała | 1 | -1/+1 | |
Not all systems put Python binary in /usr/bin; fix it as usual by using env(1) | |||||
2018-04-25 | Add proposed FENCE.TSO encoding | Andrew Waterman | 1 | -0/+3 | |
2017-12-27 | Use old C style comments. (#18) | Tim Newsome | 1 | -11/+11 | |
This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier. | |||||
2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 2 | -18/+18 | |
Closes #17 | |||||
2017-11-27 | Don't copy encoding.h to binutils anymore | Andrew Waterman | 1 | -4/+0 | |
Now that binutils is upstream, we maintain that file manually. | |||||
2017-11-27 | Generate encoding.h for OpenOCD as well. (#16) | Tim Newsome | 1 | -2/+3 | |
2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 5 | -48/+87 | |