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AgeCommit message (Expand)AuthorFilesLines
2017-05-07SB->B; UJ->JAndrew Waterman1-2/+2
2017-05-07Add UXl/SXLAndrew Waterman1-0/+3
2017-04-25Add ECALL/EBREAK to privileged instruction tableAndrew Waterman1-0/+2
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman3-4/+8
2017-04-25Remove hret instructionAndrew Waterman2-2/+1
2017-03-31Add LICENSEAndrew Waterman1-0/+24
2017-03-31Support generating Go code (#3)Benjamin Barenblat3-0/+45
2017-03-30New PMP encodingAndrew Waterman1-5/+6
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman2-6/+8
2017-03-23Add PMPAndrew Waterman2-1/+32
2017-03-23Add TW/TVM/TSR fields to mstatusAndrew Waterman1-1/+4
2017-03-09New counter-enable mechanismAndrew Waterman1-2/+2
2017-03-09Update SPTBR fieldsAndrew Waterman1-14/+9
2017-02-20Use gcc csr register constraintAndrew Waterman1-16/+4
2017-02-20Remove sfence.vm and add sfence.vmaAndrew Waterman2-6/+4
2017-02-20Drop mstatus.VM fieldAndrew Waterman1-1/+0
2017-02-14Don't update binutils' riscv-opc.h automatically anymoreAndrew Waterman1-1/+1
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-0/+14
2016-12-21Add Q extensionKito Cheng1-0/+39
2016-12-21Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 spaceKito Cheng1-1/+1
2016-12-06avoid non-standard predefined macrosAndrew Waterman1-1/+1
2016-08-26Renumber misa; add performance counter CSRsAndrew Waterman1-33/+154
2016-08-26Add mcontrol type constants. (#11)Tim Newsome1-0/+3
2016-08-25Re-rename trigger registers to be 1-basedAndrew Waterman1-3/+3
2016-08-25Make hardware triggers match latest spec.Tim Newsome2-22/+34
2016-07-06Update to new PTE formatAndrew Waterman1-33/+10
2016-06-30Remove instructions from privilege spec that are already in user specAndrew Waterman1-5/+2
2016-06-18Add READMEAndrew Waterman1-0/+10
2016-06-17Remove sasid (it's merged into sptbr now)Andrew Waterman1-1/+0
2016-06-09Update breakpoint specAndrew Waterman1-8/+15
2016-06-08Add breakpoint CSRsAndrew Waterman2-0/+14
2016-06-03Keep DCSR_XDEBUGVER unsigned.Tim Newsome1-1/+1
2016-06-01Update path to binutilsAndrew Waterman1-1/+1
2016-06-01Add dret instruction and debug CSRs. (#5)Tim Newsome3-0/+27
2016-05-13Remove arg lists from latex tablesAndrew Waterman1-42/+1
2016-05-13Rename "Device Interrupt" to "External Interrupt"Andrew Waterman1-3/+6
2016-05-02Remove mipi registersAndrew Waterman1-1/+0
2016-05-02Remove tohost/fromhostAndrew Waterman1-2/+0
2016-04-30Remove mcfgaddr; change memory mapAndrew Waterman2-5/+7
2016-04-30Remove mtimecmpAndrew Waterman1-2/+0
2016-04-30ERET -> xRETAndrew Waterman3-7/+9
2016-04-06Remove nonstandard stats, uarch CSRsAndrew Waterman1-21/+0
2016-03-10Allow immediates for write_csr; check for signednessAndrew Waterman1-6/+12
2016-03-10Reflect new location of encoding.h in riscv-pkAndrew Waterman1-1/+1
2016-03-03Update CSR encodingAndrew Waterman2-2/+24
2016-02-28WIP on priv spec v1.9Andrew Waterman1-30/+14
2016-02-28WIP on priv spec v1.9Andrew Waterman2-21/+21
2016-02-05WIP on priv spec v1.9Andrew Waterman3-44/+44
2016-01-13remove hwachaV3 definitionsColin Schmidt4-194/+1
2015-11-12add miobase, mipi; drop send_ipiAndrew Waterman1-1/+2