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Author
Files
Lines
2018-09-10
Include RVC pseudos in chisel decoder
Andrew Waterman
1
-1
/
+1
2018-08-25
Improve TeX output for FENCE instructions
Andrew Waterman
2
-3
/
+3
2018-08-06
FENCE has a field called FM in bits 31:28
Andrew Waterman
2
-2
/
+3
2018-07-17
Make the hashbang portable (#20)
Edward Tomasz NapieraĆa
1
-1
/
+1
2018-04-25
Add proposed FENCE.TSO encoding
Andrew Waterman
1
-0
/
+3
2017-12-27
Use old C style comments. (#18)
Tim Newsome
1
-11
/
+11
2017-11-27
Rename sptbr to satp and sbadaddr to stval
Andrew Waterman
2
-18
/
+18
2017-11-27
Don't copy encoding.h to binutils anymore
Andrew Waterman
1
-4
/
+0
2017-11-27
Generate encoding.h for OpenOCD as well. (#16)
Tim Newsome
1
-2
/
+3
2017-05-17
Merge remote-tracking branch 'origin/priv-1.10'
Palmer Dabbelt
5
-48
/
+87
2017-05-07
SB->B; UJ->J
Andrew Waterman
1
-2
/
+2
2017-05-07
Add UXl/SXL
Andrew Waterman
1
-0
/
+3
2017-04-25
Add ECALL/EBREAK to privileged instruction table
Andrew Waterman
1
-0
/
+2
2017-04-25
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman
3
-4
/
+8
2017-04-25
Remove hret instruction
Andrew Waterman
2
-2
/
+1
2017-03-31
Add LICENSE
Andrew Waterman
1
-0
/
+24
2017-03-31
Support generating Go code (#3)
Benjamin Barenblat
3
-0
/
+45
2017-03-30
New PMP encoding
Andrew Waterman
1
-5
/
+6
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
2
-6
/
+8
2017-03-23
Add PMP
Andrew Waterman
2
-1
/
+32
2017-03-23
Add TW/TVM/TSR fields to mstatus
Andrew Waterman
1
-1
/
+4
2017-03-09
New counter-enable mechanism
Andrew Waterman
1
-2
/
+2
2017-03-09
Update SPTBR fields
Andrew Waterman
1
-14
/
+9
2017-02-20
Use gcc csr register constraint
Andrew Waterman
1
-16
/
+4
2017-02-20
Remove sfence.vm and add sfence.vma
Andrew Waterman
2
-6
/
+4
2017-02-20
Drop mstatus.VM field
Andrew Waterman
1
-1
/
+0
2017-02-14
Don't update binutils' riscv-opc.h automatically anymore
Andrew Waterman
1
-1
/
+1
2017-02-08
Encode VM type in sptbr, not mstatus
Andrew Waterman
1
-0
/
+14
2016-12-21
Add Q extension
Kito Cheng
1
-0
/
+39
2016-12-21
Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space
Kito Cheng
1
-1
/
+1
2016-12-06
avoid non-standard predefined macros
Andrew Waterman
1
-1
/
+1
2016-08-26
Renumber misa; add performance counter CSRs
Andrew Waterman
1
-33
/
+154
2016-08-26
Add mcontrol type constants. (#11)
Tim Newsome
1
-0
/
+3
2016-08-25
Re-rename trigger registers to be 1-based
Andrew Waterman
1
-3
/
+3
2016-08-25
Make hardware triggers match latest spec.
Tim Newsome
2
-22
/
+34
2016-07-06
Update to new PTE format
Andrew Waterman
1
-33
/
+10
2016-06-30
Remove instructions from privilege spec that are already in user spec
Andrew Waterman
1
-5
/
+2
2016-06-18
Add README
Andrew Waterman
1
-0
/
+10
2016-06-17
Remove sasid (it's merged into sptbr now)
Andrew Waterman
1
-1
/
+0
2016-06-09
Update breakpoint spec
Andrew Waterman
1
-8
/
+15
2016-06-08
Add breakpoint CSRs
Andrew Waterman
2
-0
/
+14
2016-06-03
Keep DCSR_XDEBUGVER unsigned.
Tim Newsome
1
-1
/
+1
2016-06-01
Update path to binutils
Andrew Waterman
1
-1
/
+1
2016-06-01
Add dret instruction and debug CSRs. (#5)
Tim Newsome
3
-0
/
+27
2016-05-13
Remove arg lists from latex tables
Andrew Waterman
1
-42
/
+1
2016-05-13
Rename "Device Interrupt" to "External Interrupt"
Andrew Waterman
1
-3
/
+6
2016-05-02
Remove mipi registers
Andrew Waterman
1
-1
/
+0
2016-05-02
Remove tohost/fromhost
Andrew Waterman
1
-2
/
+0
2016-04-30
Remove mcfgaddr; change memory map
Andrew Waterman
2
-5
/
+7
2016-04-30
Remove mtimecmp
Andrew Waterman
1
-2
/
+0
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