riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-04-23	Updated path to FESVR_H in Makefile (#25)	Torbjørn	1	-1/+1
2019-04-22	Add missing N-extension CSRs	Andrew Waterman	1	-0/+8
2019-02-28	Read opcodes from files (#23)	Pavel I. Kryukov	1	-61/+74
2019-02-11	Add SystemVerilog generation (#24)	Florian Zaruba	2	-0/+24
2019-01-22	Add tentative CSR assignment for fast-interrupt group's CLIC proposal	Andrew Waterman	1	-0/+17
2019-01-21	Add tentative hypervisor CSR and instruction encodings	Andrew Waterman	2	-1/+23
2018-11-20	Don't label latex tables	Andrew Waterman	1	-1/+0
2018-11-20	Exclude ECALL/EBREAK from privileged instruction table	Andrew Waterman	1	-3/+1
2018-11-19	Modernize to Python 3 (#22)	Pavel I. Kryukov	1	-111/+114
2018-11-06	Separate FENCE.I and CSRRx from RV32I table	Andrew Waterman	1	-9/+15
2018-09-20	Add header following Go convention for generated code (#21)	Tobias Klauser	1	-1/+1
2018-09-10	Include RVC pseudos in chisel decoder	Andrew Waterman	1	-1/+1
2018-08-25	Improve TeX output for FENCE instructions	Andrew Waterman	2	-3/+3
2018-08-06	FENCE has a field called FM in bits 31:28	Andrew Waterman	2	-2/+3
2018-07-17	Make the hashbang portable (#20)	Edward Tomasz Napierała	1	-1/+1
2018-04-25	Add proposed FENCE.TSO encoding	Andrew Waterman	1	-0/+3
2017-12-27	Use old C style comments. (#18)	Tim Newsome	1	-11/+11
2017-11-27	Rename sptbr to satp and sbadaddr to stval	Andrew Waterman	2	-18/+18
2017-11-27	Don't copy encoding.h to binutils anymore	Andrew Waterman	1	-4/+0
2017-11-27	Generate encoding.h for OpenOCD as well. (#16)	Tim Newsome	1	-2/+3
2017-05-17	Merge remote-tracking branch 'origin/priv-1.10'	Palmer Dabbelt	5	-48/+87
2017-05-07	SB->B; UJ->J	Andrew Waterman	1	-2/+2
2017-05-07	Add UXl/SXL	Andrew Waterman	1	-0/+3
2017-04-25	Add ECALL/EBREAK to privileged instruction table	Andrew Waterman	1	-0/+2
2017-04-25	FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X	Andrew Waterman	3	-4/+8
2017-04-25	Remove hret instruction	Andrew Waterman	2	-2/+1
2017-03-31	Add LICENSE	Andrew Waterman	1	-0/+24
2017-03-31	Support generating Go code (#3)	Benjamin Barenblat	3	-0/+45
2017-03-30	New PMP encoding	Andrew Waterman	1	-5/+6
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	2	-6/+8
2017-03-23	Add PMP	Andrew Waterman	2	-1/+32
2017-03-23	Add TW/TVM/TSR fields to mstatus	Andrew Waterman	1	-1/+4
2017-03-09	New counter-enable mechanism	Andrew Waterman	1	-2/+2
2017-03-09	Update SPTBR fields	Andrew Waterman	1	-14/+9
2017-02-20	Use gcc csr register constraint	Andrew Waterman	1	-16/+4
2017-02-20	Remove sfence.vm and add sfence.vma	Andrew Waterman	2	-6/+4
2017-02-20	Drop mstatus.VM field	Andrew Waterman	1	-1/+0
2017-02-14	Don't update binutils' riscv-opc.h automatically anymore	Andrew Waterman	1	-1/+1
2017-02-08	Encode VM type in sptbr, not mstatus	Andrew Waterman	1	-0/+14
2016-12-21	Add Q extension	Kito Cheng	1	-0/+39
2016-12-21	Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space	Kito Cheng	1	-1/+1
2016-12-06	avoid non-standard predefined macros	Andrew Waterman	1	-1/+1
2016-08-26	Renumber misa; add performance counter CSRs	Andrew Waterman	1	-33/+154
2016-08-26	Add mcontrol type constants. (#11)	Tim Newsome	1	-0/+3
2016-08-25	Re-rename trigger registers to be 1-based	Andrew Waterman	1	-3/+3
2016-08-25	Make hardware triggers match latest spec.	Tim Newsome	2	-22/+34
2016-07-06	Update to new PTE format	Andrew Waterman	1	-33/+10
2016-06-30	Remove instructions from privilege spec that are already in user spec	Andrew Waterman	1	-5/+2
2016-06-18	Add README	Andrew Waterman	1	-0/+10
2016-06-17	Remove sasid (it's merged into sptbr now)	Andrew Waterman	1	-1/+0