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riscv-tools/riscv-opcodes.git
confprec
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incoresemi-migration-to-new-format
latex-based-output-refactor
llvm-encodings
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2020-07-27
rvv: add whole ldst pseudo instruction and update reference link
Chih-Min Chao
2
-1
/
+6
2020-07-21
Add vrgatherei16.vv
Andrew Waterman
1
-10
/
+11
2020-07-21
Incorporate whole-register load/store changes in RVV v1.0-draft
Andrew Waterman
1
-2
/
+20
2020-06-10
Rebase d242e1ed7 onto master
Andrew Waterman
3
-1
/
+133
2020-05-12
RVV v0.9: AMOs with explicit element widths
Andrew Waterman
1
-19
/
+39
2020-05-12
RVV v0.9: loads/stores with explicit element widths
Andrew Waterman
1
-45
/
+33
2020-05-12
RVV v0.9: change vl1r/vs1r opcodes
Andrew Waterman
1
-2
/
+2
2020-05-12
RVV v0.9: new extension instructions
Andrew Waterman
1
-0
/
+9
2020-05-12
RVV v0.9: move VFUNARY0/VFUNARY1 opcodes
Andrew Waterman
1
-26
/
+26
2020-05-04
Add DCSR_CAUSE_GROUP. (#44)
Tim Newsome
1
-0
/
+1
2020-04-14
rvv: add new vcsr for vector spec 0.9 (#42)
Chih-Min Chao
1
-0
/
+1
2020-04-07
Remove RV128 for now, because it is quite speculative
Andrew Waterman
3
-13
/
+2
2020-03-31
update csr to draft-20200326-af69f79 (#39)
Chih-Min Chao
1
-1
/
+16
2020-03-29
Using OrderedDict to keep encodings for match/mask. (#38)
Kito Cheng
1
-2
/
+3
2020-03-28
Add FP->int truncating conversions
Andrew Waterman
1
-17
/
+23
2020-03-28
Add vfslide1up/down
Andrew Waterman
1
-8
/
+10
2020-03-03
Factor out RVC opcodes into per-extension files
Andrew Waterman
6
-31
/
+37
2020-03-03
Factor out opcodes into per-extension files
Andrew Waterman
16
-249
/
+264
2020-03-03
Clean up Makefile
Andrew Waterman
1
-9
/
+12
2020-02-28
Add mcountinhibit CSR
Andrew Waterman
1
-0
/
+1
2020-02-24
Add N-extension CSRs and status bits. (#37)
michael-roe
2
-0
/
+11
2020-02-13
Remove mstatus.HPP; move mstatus.VS to its old location
Andrew Waterman
1
-3
/
+2
2019-11-28
Remove vamo*q; replace vamo*d with vamo*e
Andrew Waterman
1
-19
/
+9
2019-11-28
Add vmv<nf>r.v
Andrew Waterman
2
-0
/
+6
2019-11-28
Merge branch 'chihminchao-rvv-0.8-draft-20191118'
Andrew Waterman
3
-20
/
+37
2019-11-28
rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wi
Chih-Min Chao
1
-12
/
+12
2019-11-28
rvv: add load/store whole register
Chih-Min Chao
1
-2
/
+7
2019-11-28
rvv: replace vfncvt suffix with .w
Chih-Min Chao
1
-6
/
+6
2019-11-28
rvv: add vqmacc variant insn
Chih-Min Chao
1
-0
/
+9
2019-11-28
rvv: add vleb csr register and mstatus.vs field
Chih-Min Chao
2
-0
/
+3
2019-11-15
Remove scaled fixed-point multiply-add instructions
Andrew Waterman
1
-8
/
+0
2019-11-15
vcompress is encoded with vm=1
Andrew Waterman
1
-1
/
+1
2019-11-15
Add vaaddu/vasubu; change vaadd/vasub opcodes
Andrew Waterman
1
-5
/
+10
2019-11-11
Update encoding of vadc and friends
Andrew Waterman
1
-10
/
+10
2019-11-11
Add vfncvt.rod.f.f.v instruction
Andrew Waterman
1
-5
/
+6
2019-09-17
vwmaccsu/us opcodes have been swapped
Andrew Waterman
1
-6
/
+6
2019-09-12
fesvr no longer needs encoding.h
Andrew Waterman
1
-3
/
+2
2019-09-12
Add PAUSE hint instruction
Andrew Waterman
1
-0
/
+1
2019-08-26
More updates to rvv encoding
Andrew Waterman
1
-13
/
+11
2019-08-03
Fix crash introduced by #30
Andrew Waterman
1
-1
/
+1
2019-08-03
(Partially) fix #30 (#31)
Tommy Thorn
3
-42
/
+47
2019-07-15
vext.x.v -> vmv.x.s
Andrew Waterman
1
-1
/
+1
2019-07-05
Fix encoding of vfclass.v instruction
Andrew Waterman
1
-1
/
+1
2019-06-28
vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcode
Andrew Waterman
1
-2
/
+2
2019-06-19
Remove redundant entry from Makefile
Andrew Waterman
1
-1
/
+1
2019-06-18
v-spec 0.7.1-0607 (#29)
Chih-Min Chao
2
-41
/
+74
2019-06-18
Add pseudos for RV32 shifts with correct immediate constraint
Andrew Waterman
2
-1
/
+6
2019-06-16
More hypervisor v0.4 updates
Andrew Waterman
2
-3
/
+3
2019-06-16
Updates for hypervisor v0.4
Andrew Waterman
1
-13
/
+14
2019-06-11
Expand vfunary0 and vfunary1 opcodes into sub-instructions
Andrew Waterman
1
-2
/
+20
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