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riscv-tools/riscv-opcodes.git
confprec
debug
incoresemi-migration-to-new-format
latex-based-output-refactor
llvm-encodings
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mvp
riscv-bitmanip
rnmi
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Files
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2020-03-03
Clean up Makefile
Andrew Waterman
1
-9
/
+12
2020-02-28
Add mcountinhibit CSR
Andrew Waterman
1
-0
/
+1
2020-02-24
Add N-extension CSRs and status bits. (#37)
michael-roe
2
-0
/
+11
2020-02-13
Remove mstatus.HPP; move mstatus.VS to its old location
Andrew Waterman
1
-3
/
+2
2019-11-28
Remove vamo*q; replace vamo*d with vamo*e
Andrew Waterman
1
-19
/
+9
2019-11-28
Add vmv<nf>r.v
Andrew Waterman
2
-0
/
+6
2019-11-28
Merge branch 'chihminchao-rvv-0.8-draft-20191118'
Andrew Waterman
3
-20
/
+37
2019-11-28
rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wi
Chih-Min Chao
1
-12
/
+12
2019-11-28
rvv: add load/store whole register
Chih-Min Chao
1
-2
/
+7
2019-11-28
rvv: replace vfncvt suffix with .w
Chih-Min Chao
1
-6
/
+6
2019-11-28
rvv: add vqmacc variant insn
Chih-Min Chao
1
-0
/
+9
2019-11-28
rvv: add vleb csr register and mstatus.vs field
Chih-Min Chao
2
-0
/
+3
2019-11-15
Remove scaled fixed-point multiply-add instructions
Andrew Waterman
1
-8
/
+0
2019-11-15
vcompress is encoded with vm=1
Andrew Waterman
1
-1
/
+1
2019-11-15
Add vaaddu/vasubu; change vaadd/vasub opcodes
Andrew Waterman
1
-5
/
+10
2019-11-11
Update encoding of vadc and friends
Andrew Waterman
1
-10
/
+10
2019-11-11
Add vfncvt.rod.f.f.v instruction
Andrew Waterman
1
-5
/
+6
2019-09-17
vwmaccsu/us opcodes have been swapped
Andrew Waterman
1
-6
/
+6
2019-09-12
fesvr no longer needs encoding.h
Andrew Waterman
1
-3
/
+2
2019-09-12
Add PAUSE hint instruction
Andrew Waterman
1
-0
/
+1
2019-08-26
More updates to rvv encoding
Andrew Waterman
1
-13
/
+11
2019-08-03
Fix crash introduced by #30
Andrew Waterman
1
-1
/
+1
2019-08-03
(Partially) fix #30 (#31)
Tommy Thorn
3
-42
/
+47
2019-07-15
vext.x.v -> vmv.x.s
Andrew Waterman
1
-1
/
+1
2019-07-05
Fix encoding of vfclass.v instruction
Andrew Waterman
1
-1
/
+1
2019-06-28
vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcode
Andrew Waterman
1
-2
/
+2
2019-06-19
Remove redundant entry from Makefile
Andrew Waterman
1
-1
/
+1
2019-06-18
v-spec 0.7.1-0607 (#29)
Chih-Min Chao
2
-41
/
+74
2019-06-18
Add pseudos for RV32 shifts with correct immediate constraint
Andrew Waterman
2
-1
/
+6
2019-06-16
More hypervisor v0.4 updates
Andrew Waterman
2
-3
/
+3
2019-06-16
Updates for hypervisor v0.4
Andrew Waterman
1
-13
/
+14
2019-06-11
Expand vfunary0 and vfunary1 opcodes into sub-instructions
Andrew Waterman
1
-2
/
+20
2019-06-05
More V 0.7.1 updates
Andrew Waterman
1
-12
/
+10
2019-06-05
Some V 0.7.1 updates
Andrew Waterman
2
-19
/
+18
2019-06-05
VMV.S.X requires vs2=0
Andrew Waterman
1
-2
/
+2
2019-05-17
Merge branch 'chihminchao-rvv-spec-0.7'
Andrew Waterman
4
-4
/
+414
2019-05-17
Expand vmunary0 into its constituent instructions
Andrew Waterman
1
-1
/
+6
2019-05-17
vmv/vext/vfmv are reserved when vm=0
Andrew Waterman
1
-4
/
+4
2019-05-17
vadc/vsbc require vm=1
Andrew Waterman
1
-5
/
+5
2019-05-17
Add pseudos for masked/unmasked vmerge to help with decoding
Andrew Waterman
2
-2
/
+12
2019-05-16
rvv: vector instruction encoding
Chih-Min Chao
2
-2
/
+380
2019-05-16
rvv: add vector register field and control register
Chih-Min Chao
1
-1
/
+18
2019-05-14
zimm -> uimm in CSR instruction listing
Andrew Waterman
1
-2
/
+2
2019-04-26
Create RVQ listing in latex table
Andrew Waterman
1
-0
/
+16
2019-04-24
Add RV128 opcodes (#26)
Rustem Yunusov
2
-4
/
+10
2019-04-23
Updated path to FESVR_H in Makefile (#25)
Torbjørn
1
-1
/
+1
2019-04-22
Add missing N-extension CSRs
Andrew Waterman
1
-0
/
+8
2019-02-28
Read opcodes from files (#23)
Pavel I. Kryukov
1
-61
/
+74
2019-02-11
Add SystemVerilog generation (#24)
Florian Zaruba
2
-0
/
+24
2019-01-22
Add tentative CSR assignment for fast-interrupt group's CLIC proposal
Andrew Waterman
1
-0
/
+17
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