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2021-01-08Update Zba/Zbc/Zbs mnemonics to v0.93; Zbe to v0.94-draftAndrew Waterman2-19/+19
2021-01-08Add Zsn to encoding.hAndrew Waterman1-0/+1
2021-01-08Update mstatus/sstatus fields for hypervisor v0.6Andrew Waterman1-2/+8
2020-12-02Merge pull request #55 from chihminchao/rvv-pre-1.0-index-and-quadAndrew Waterman1-31/+36
2020-12-02rvv: follow change of indexed ordered/unordered load/storeChih-Min Chao1-26/+36
2020-12-02rvv: remove quad instructionsChih-Min Chao1-5/+0
2020-11-20Remove instructions already removed from RV64BAndrew Waterman1-7/+0
2020-11-13Merge branch 'riscv-bitmanip'Andrew Waterman3-1/+132
2020-11-13Remove subu.wriscv-bitmanipAndrew Waterman1-1/+0
2020-11-13Update minu/max encodingsAndrew Waterman1-2/+2
2020-11-09Add GitHub Actions file (#53)Pavel I. Kryukov1-0/+21
2020-11-08Support generating Rust code (#52)Ngo Iok Ui (Wu Yu Wei)2-0/+16
2020-10-14Adding four trigger CSRs to the list (#50)Jan Matyas1-0/+4
2020-09-17Add encodings of vfrsqrte7.v and vfrece7.v (#49)Zhen Wei1-0/+2
2020-08-21Add header to .h files. (#48)Tim Newsome1-1/+6
2020-08-03Make *.vv operand naming be consistent with type (#46)Zhen Wei1-48/+48
2020-07-31Merge pull request #45 from chihminchao/rvv-and-hypervisorAndrew Waterman8-47/+141
2020-07-31hyperviosr: add csr mask and interrupt macro nameChih-Min Chao6-13/+70
2020-07-27rvv: add eew 128 ~ 1024 load/store opcodeChih-Min Chao1-33/+65
2020-07-27rvv: add whole ldst pseudo instruction and update reference linkChih-Min Chao2-1/+6
2020-07-21Add vrgatherei16.vvAndrew Waterman1-10/+11
2020-07-21Incorporate whole-register load/store changes in RVV v1.0-draftAndrew Waterman1-2/+20
2020-06-10Rebase d242e1ed7 onto masterAndrew Waterman3-1/+133
2020-05-12RVV v0.9: AMOs with explicit element widthsAndrew Waterman1-19/+39
2020-05-12RVV v0.9: loads/stores with explicit element widthsAndrew Waterman1-45/+33
2020-05-12RVV v0.9: change vl1r/vs1r opcodesAndrew Waterman1-2/+2
2020-05-12RVV v0.9: new extension instructionsAndrew Waterman1-0/+9
2020-05-12RVV v0.9: move VFUNARY0/VFUNARY1 opcodesAndrew Waterman1-26/+26
2020-05-04Add DCSR_CAUSE_GROUP. (#44)Tim Newsome1-0/+1
2020-04-14rvv: add new vcsr for vector spec 0.9 (#42)Chih-Min Chao1-0/+1
2020-04-07Remove RV128 for now, because it is quite speculativeAndrew Waterman3-13/+2
2020-03-31update csr to draft-20200326-af69f79 (#39)Chih-Min Chao1-1/+16
2020-03-29Using OrderedDict to keep encodings for match/mask. (#38)Kito Cheng1-2/+3
2020-03-28Add FP->int truncating conversionsAndrew Waterman1-17/+23
2020-03-28Add vfslide1up/downAndrew Waterman1-8/+10
2020-03-03Factor out RVC opcodes into per-extension filesAndrew Waterman6-31/+37
2020-03-03Factor out opcodes into per-extension filesAndrew Waterman16-249/+264
2020-03-03Clean up MakefileAndrew Waterman1-9/+12
2020-02-28Add mcountinhibit CSRAndrew Waterman1-0/+1
2020-02-24Add N-extension CSRs and status bits. (#37)michael-roe2-0/+11
2020-02-13Remove mstatus.HPP; move mstatus.VS to its old locationAndrew Waterman1-3/+2
2019-11-28Remove vamo*q; replace vamo*d with vamo*eAndrew Waterman1-19/+9
2019-11-28Add vmv<nf>r.vAndrew Waterman2-0/+6
2019-11-28Merge branch 'chihminchao-rvv-0.8-draft-20191118'Andrew Waterman3-20/+37
2019-11-28rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wiChih-Min Chao1-12/+12
2019-11-28rvv: add load/store whole registerChih-Min Chao1-2/+7
2019-11-28rvv: replace vfncvt suffix with .wChih-Min Chao1-6/+6
2019-11-28rvv: add vqmacc variant insnChih-Min Chao1-0/+9
2019-11-28rvv: add vleb csr register and mstatus.vs fieldChih-Min Chao2-0/+3
2019-11-15Remove scaled fixed-point multiply-add instructionsAndrew Waterman1-8/+0
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