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2019-06-05Some V 0.7.1 updatesAndrew Waterman2-19/+18
2019-06-05VMV.S.X requires vs2=0Andrew Waterman1-2/+2
2019-05-17Merge branch 'chihminchao-rvv-spec-0.7'Andrew Waterman4-4/+414
2019-05-17Expand vmunary0 into its constituent instructionsAndrew Waterman1-1/+6
Note that vmiota is being renamed to viota: https://github.com/riscv/riscv-v-spec/pull/180
2019-05-17vmv/vext/vfmv are reserved when vm=0Andrew Waterman1-4/+4
This is not currently stated in the spec, but there is a pull request to make this explicit: https://github.com/riscv/riscv-v-spec/pull/179
2019-05-17vadc/vsbc require vm=1Andrew Waterman1-5/+5
2019-05-17Add pseudos for masked/unmasked vmerge to help with decodingAndrew Waterman2-2/+12
2019-05-16rvv: vector instruction encodingChih-Min Chao2-2/+380
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-16rvv: add vector register field and control registerChih-Min Chao1-1/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-2/+2
2019-04-26Create RVQ listing in latex tableAndrew Waterman1-0/+16
2019-04-24Add RV128 opcodes (#26)Rustem Yunusov2-4/+10
2019-04-23Updated path to FESVR_H in Makefile (#25)Torbjørn1-1/+1
2019-04-22Add missing N-extension CSRsAndrew Waterman1-0/+8
2019-02-28Read opcodes from files (#23)Pavel I. Kryukov1-61/+74
Current generation flow assumes that opcodes are provided in a `cat ./opcodes | ./parse_opcodes -c' manner. However, Windows CMD has no `cat' command, and it uses `type' instead, so implementation of cross-platform script is complicated. In this patch, we allow parsing opcode files directly by Python, if their names are provided as a command line arguments, not depending on the host shell. If no arguments are passed, script behaves as usual, reading opcodes from the stdin.
2019-02-11Add SystemVerilog generation (#24)Florian Zaruba2-0/+24
2019-01-22Add tentative CSR assignment for fast-interrupt group's CLIC proposalAndrew Waterman1-0/+17
2019-01-21Add tentative hypervisor CSR and instruction encodingsAndrew Waterman2-1/+23
2018-11-20Don't label latex tablesAndrew Waterman1-1/+0
2018-11-20Exclude ECALL/EBREAK from privileged instruction tableAndrew Waterman1-3/+1
2018-11-19Modernize to Python 3 (#22)Pavel I. Kryukov1-111/+114
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-9/+15
2018-09-20Add header following Go convention for generated code (#21)Tobias Klauser1-1/+1
Go has a convention for generated code comments (https://golang.org/s/generatedcode), i.e. they must match the regex ^// Code generated .* DO NOT EDIT\.$ Adjust the generated header to follow this convention.
2018-09-10Include RVC pseudos in chisel decoderAndrew Waterman1-1/+1
2018-08-25Improve TeX output for FENCE instructionsAndrew Waterman2-3/+3
2018-08-06FENCE has a field called FM in bits 31:28Andrew Waterman2-2/+3
2018-07-17Make the hashbang portable (#20)Edward Tomasz Napierała1-1/+1
Not all systems put Python binary in /usr/bin; fix it as usual by using env(1)
2018-04-25Add proposed FENCE.TSO encodingAndrew Waterman1-0/+3
2017-12-27Use old C style comments. (#18)Tim Newsome1-11/+11
This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier.
2017-11-27Rename sptbr to satp and sbadaddr to stvalAndrew Waterman2-18/+18
Closes #17
2017-11-27Don't copy encoding.h to binutils anymoreAndrew Waterman1-4/+0
Now that binutils is upstream, we maintain that file manually.
2017-11-27Generate encoding.h for OpenOCD as well. (#16)Tim Newsome1-2/+3
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt5-48/+87
2017-05-07SB->B; UJ->JAndrew Waterman1-2/+2
2017-05-07Add UXl/SXLAndrew Waterman1-0/+3
2017-04-25Add ECALL/EBREAK to privileged instruction tableAndrew Waterman1-0/+2
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman3-4/+8
2017-04-25Remove hret instructionAndrew Waterman2-2/+1
2017-03-31Add LICENSEAndrew Waterman1-0/+24
2017-03-31Support generating Go code (#3)Benjamin Barenblat3-0/+45
* Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler.
2017-03-30New PMP encodingAndrew Waterman1-5/+6
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman2-6/+8
2017-03-23Add PMPAndrew Waterman2-1/+32
2017-03-23Add TW/TVM/TSR fields to mstatusAndrew Waterman1-1/+4
2017-03-09New counter-enable mechanismAndrew Waterman1-2/+2
2017-03-09Update SPTBR fieldsAndrew Waterman1-14/+9
2017-02-20Use gcc csr register constraintAndrew Waterman1-16/+4
2017-02-20Remove sfence.vm and add sfence.vmaAndrew Waterman2-6/+4
2017-02-20Drop mstatus.VM fieldAndrew Waterman1-1/+0
2017-02-14Don't update binutils' riscv-opc.h automatically anymoreAndrew Waterman1-1/+1
It's upstreamed, so avoid the false impression it can easily change.
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