Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2019-06-05 | Some V 0.7.1 updates | Andrew Waterman | 2 | -19/+18 | |
2019-06-05 | VMV.S.X requires vs2=0 | Andrew Waterman | 1 | -2/+2 | |
2019-05-17 | Merge branch 'chihminchao-rvv-spec-0.7' | Andrew Waterman | 4 | -4/+414 | |
2019-05-17 | Expand vmunary0 into its constituent instructions | Andrew Waterman | 1 | -1/+6 | |
Note that vmiota is being renamed to viota: https://github.com/riscv/riscv-v-spec/pull/180 | |||||
2019-05-17 | vmv/vext/vfmv are reserved when vm=0 | Andrew Waterman | 1 | -4/+4 | |
This is not currently stated in the spec, but there is a pull request to make this explicit: https://github.com/riscv/riscv-v-spec/pull/179 | |||||
2019-05-17 | vadc/vsbc require vm=1 | Andrew Waterman | 1 | -5/+5 | |
2019-05-17 | Add pseudos for masked/unmasked vmerge to help with decoding | Andrew Waterman | 2 | -2/+12 | |
2019-05-16 | rvv: vector instruction encoding | Chih-Min Chao | 2 | -2/+380 | |
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-16 | rvv: add vector register field and control register | Chih-Min Chao | 1 | -1/+18 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-14 | zimm -> uimm in CSR instruction listing | Andrew Waterman | 1 | -2/+2 | |
2019-04-26 | Create RVQ listing in latex table | Andrew Waterman | 1 | -0/+16 | |
2019-04-24 | Add RV128 opcodes (#26) | Rustem Yunusov | 2 | -4/+10 | |
2019-04-23 | Updated path to FESVR_H in Makefile (#25) | Torbjørn | 1 | -1/+1 | |
2019-04-22 | Add missing N-extension CSRs | Andrew Waterman | 1 | -0/+8 | |
2019-02-28 | Read opcodes from files (#23) | Pavel I. Kryukov | 1 | -61/+74 | |
Current generation flow assumes that opcodes are provided in a `cat ./opcodes | ./parse_opcodes -c' manner. However, Windows CMD has no `cat' command, and it uses `type' instead, so implementation of cross-platform script is complicated. In this patch, we allow parsing opcode files directly by Python, if their names are provided as a command line arguments, not depending on the host shell. If no arguments are passed, script behaves as usual, reading opcodes from the stdin. | |||||
2019-02-11 | Add SystemVerilog generation (#24) | Florian Zaruba | 2 | -0/+24 | |
2019-01-22 | Add tentative CSR assignment for fast-interrupt group's CLIC proposal | Andrew Waterman | 1 | -0/+17 | |
2019-01-21 | Add tentative hypervisor CSR and instruction encodings | Andrew Waterman | 2 | -1/+23 | |
2018-11-20 | Don't label latex tables | Andrew Waterman | 1 | -1/+0 | |
2018-11-20 | Exclude ECALL/EBREAK from privileged instruction table | Andrew Waterman | 1 | -3/+1 | |
2018-11-19 | Modernize to Python 3 (#22) | Pavel I. Kryukov | 1 | -111/+114 | |
2018-11-06 | Separate FENCE.I and CSRRx from RV32I table | Andrew Waterman | 1 | -9/+15 | |
2018-09-20 | Add header following Go convention for generated code (#21) | Tobias Klauser | 1 | -1/+1 | |
Go has a convention for generated code comments (https://golang.org/s/generatedcode), i.e. they must match the regex ^// Code generated .* DO NOT EDIT\.$ Adjust the generated header to follow this convention. | |||||
2018-09-10 | Include RVC pseudos in chisel decoder | Andrew Waterman | 1 | -1/+1 | |
2018-08-25 | Improve TeX output for FENCE instructions | Andrew Waterman | 2 | -3/+3 | |
2018-08-06 | FENCE has a field called FM in bits 31:28 | Andrew Waterman | 2 | -2/+3 | |
2018-07-17 | Make the hashbang portable (#20) | Edward Tomasz Napierała | 1 | -1/+1 | |
Not all systems put Python binary in /usr/bin; fix it as usual by using env(1) | |||||
2018-04-25 | Add proposed FENCE.TSO encoding | Andrew Waterman | 1 | -0/+3 | |
2017-12-27 | Use old C style comments. (#18) | Tim Newsome | 1 | -11/+11 | |
This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier. | |||||
2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 2 | -18/+18 | |
Closes #17 | |||||
2017-11-27 | Don't copy encoding.h to binutils anymore | Andrew Waterman | 1 | -4/+0 | |
Now that binutils is upstream, we maintain that file manually. | |||||
2017-11-27 | Generate encoding.h for OpenOCD as well. (#16) | Tim Newsome | 1 | -2/+3 | |
2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 5 | -48/+87 | |
2017-05-07 | SB->B; UJ->J | Andrew Waterman | 1 | -2/+2 | |
2017-05-07 | Add UXl/SXL | Andrew Waterman | 1 | -0/+3 | |
2017-04-25 | Add ECALL/EBREAK to privileged instruction table | Andrew Waterman | 1 | -0/+2 | |
2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 3 | -4/+8 | |
2017-04-25 | Remove hret instruction | Andrew Waterman | 2 | -2/+1 | |
2017-03-31 | Add LICENSE | Andrew Waterman | 1 | -0/+24 | |
2017-03-31 | Support generating Go code (#3) | Benjamin Barenblat | 3 | -0/+45 | |
* Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler. | |||||
2017-03-30 | New PMP encoding | Andrew Waterman | 1 | -5/+6 | |
2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 2 | -6/+8 | |
2017-03-23 | Add PMP | Andrew Waterman | 2 | -1/+32 | |
2017-03-23 | Add TW/TVM/TSR fields to mstatus | Andrew Waterman | 1 | -1/+4 | |
2017-03-09 | New counter-enable mechanism | Andrew Waterman | 1 | -2/+2 | |
2017-03-09 | Update SPTBR fields | Andrew Waterman | 1 | -14/+9 | |
2017-02-20 | Use gcc csr register constraint | Andrew Waterman | 1 | -16/+4 | |
2017-02-20 | Remove sfence.vm and add sfence.vma | Andrew Waterman | 2 | -6/+4 | |
2017-02-20 | Drop mstatus.VM field | Andrew Waterman | 1 | -1/+0 | |
2017-02-14 | Don't update binutils' riscv-opc.h automatically anymore | Andrew Waterman | 1 | -1/+1 | |
It's upstreamed, so avoid the false impression it can easily change. |