diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | inst.v | 6 | ||||
| -rw-r--r-- | instr-table.tex | 49 | ||||
| -rw-r--r-- | opcodes | 7 | ||||
| -rwxr-xr-x | parse-opcodes | 1 |
5 files changed, 58 insertions, 13 deletions
@@ -1,8 +1,9 @@ ISASIM_H := ../riscv-isa-sim/riscv/opcodes.h PK_H := ../riscv-pk/pk/riscv-opc.h -XCC_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h +GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h +XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h -install: $(ISASIM_H) $(PK_H) $(XCC_H) inst.v instr-table.tex +install: $(ISASIM_H) $(PK_H) $(GAS_H) $(XCC_H) inst.v instr-table.tex $(ISASIM_H): opcodes parse-opcodes ./parse-opcodes -isasim < $< > $@ @@ -10,6 +11,9 @@ $(ISASIM_H): opcodes parse-opcodes $(PK_H): opcodes parse-opcodes ./parse-opcodes -disasm < $< > $@ +$(GAS_H): opcodes parse-opcodes + ./parse-opcodes -disasm < $< > $@ + $(XCC_H): opcodes parse-opcodes ./parse-opcodes -disasm < $< > $@ @@ -4,7 +4,6 @@ `define JALR_C 32'b?????_?????_????????????_000_1101011 `define JALR_R 32'b?????_?????_????????????_001_1101011 `define JALR_J 32'b?????_?????_????????????_010_1101011 -`define RDNPC 32'b?????_00000_000000000000_100_1101011 `define BEQ 32'b?????_?????_?????_???????_000_1100011 `define BNE 32'b?????_?????_?????_???????_001_1100011 `define BLT 32'b?????_?????_?????_???????_100_1100011 @@ -12,6 +11,7 @@ `define BLTU 32'b?????_?????_?????_???????_110_1100011 `define BGEU 32'b?????_?????_?????_???????_111_1100011 `define LUI 32'b?????_????????????????????_0110111 +`define AUIPC 32'b?????_????????????????????_0010111 `define ADDI 32'b?????_?????_????????????_000_0010011 `define SLLI 32'b?????_?????_000000_??????_001_0010011 `define SLTI 32'b?????_?????_????????????_010_0010011 @@ -80,6 +80,10 @@ `define AMOMAX_D 32'b?????_?????_?????_0000101011_0101011 `define AMOMINU_D 32'b?????_?????_?????_0000110011_0101011 `define AMOMAXU_D 32'b?????_?????_?????_0000111011_0101011 +`define LR_W 32'b?????_?????_00000_1000000010_0101011 +`define LR_D 32'b?????_?????_00000_1000000011_0101011 +`define SC_W 32'b?????_?????_?????_1000001010_0101011 +`define SC_D 32'b?????_?????_?????_1000001011_0101011 `define FENCE_I 32'b?????_?????_????????????_001_0101111 `define FENCE 32'b?????_?????_????????????_010_0101111 `define FENCE_V_L 32'b?????_?????_????????????_100_0101111 diff --git a/instr-table.tex b/instr-table.tex index 69fff54..c1761be 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -189,15 +189,6 @@ & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & -\multicolumn{5}{c|}{000000000000} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{1101011} & RDNPC rd \\ -\cline{2-11} - - -& \multicolumn{10}{c}{} & \\ & \multicolumn{10}{c}{\bf Memory Instructions} & \\ @@ -474,6 +465,46 @@ \cline{2-11} +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & LR.W rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & LR.D rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{1000001} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & SC.W rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{1000001} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & SC.D rd,rs1,rs2 \\ +\cline{2-11} + + \end{tabular} \end{center} \end{small} @@ -12,7 +12,6 @@ jal imm25 6..2=0x1B 1..0=3 jalr.c rd rs1 imm12 9..7=0 6..2=0x1A 1..0=3 jalr.r rd rs1 imm12 9..7=1 6..2=0x1A 1..0=3 jalr.j rd rs1 imm12 9..7=2 6..2=0x1A 1..0=3 -rdnpc rd 26..22=0 21..10=0 9..7=4 6..2=0x1A 1..0=3 beq imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3 bne imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3 @@ -22,6 +21,7 @@ bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3 bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3 lui rd imm20 6..2=0x0D 1..0=3 +auipc rd imm20 6..2=0x05 1..0=3 addi rd rs1 imm12 9..7=0 6..2=0x04 1..0=3 slli rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3 @@ -104,6 +104,11 @@ amomax.d rd rs1 rs2 16..10=5 9..7=3 6..2=0x0A 1..0=3 amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x0A 1..0=3 amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3 +lr.w rd rs1 21..17=0 16=1 15..10=0 9..7=2 6..2=0x0A 1..0=3 +lr.d rd rs1 21..17=0 16=1 15..10=0 9..7=3 6..2=0x0A 1..0=3 +sc.w rd rs1 rs2 16=1 15..10=1 9..7=2 6..2=0x0A 1..0=3 +sc.d rd rs1 rs2 16=1 15..10=1 9..7=3 6..2=0x0A 1..0=3 + fence.i rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3 fence rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3 fence.v.l rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 26b8779..260634b 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -46,6 +46,7 @@ typelut[0x2B] = 4 typelut[0x2F] = 4 typelut[0x33] = 4 typelut[0x37] = 2 +typelut[0x17] = 2 typelut[0x3B] = 4 typelut[0x43] = 8 typelut[0x47] = 8 |